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1. 发明授权

US5742799A Method and apparatus for synchronizing multiple clocks 失效
标题翻译：用于同步多个时钟的方法和装置
公开(公告)号：US5742799A
公开(公告)日：1998-04-21
申请号：US801648
申请日：1997-02-18
申请人： Michael Alexander , Carmine Nicoletta , Arthur R. Piejko
发明人： Michael Alexander , Carmine Nicoletta , Arthur R. Piejko
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A method and apparatus for synchronizing multiple busses having different cycle times in a data processing system (10). The present invention synchronizes multiple clocks having different phase and frequencies without redundant use of phase lock loop units. An initial unit (7) receives an external system clock having an initial phase and frequency. An internal clock (112) is generated which is a phase and frequency adjusted derivation of the system clock. From this internal clock (112) a global clock (101) for use within the data processor (10) is generated. A second unit (9) receives the internal clock (112) and performs phase adjustment to provide a peripheral clock (114). The provision of the internal clock (112) detaches the dependency of peripheral clock (114) generation from the global clock (101), while maintaining a phase relationship with the global clock (101). In one embodiment, the present invention is implemented without the costly use of multiple phase lock loops.
摘要翻译：一种用于在数据处理系统（10）中同步具有不同周期时间的多个总线的方法和装置。本发明使具有不同相位和频率的多个时钟同步，而不需要冗余地使用锁相环单元。初始单元（7）接收具有初始相位和频率的外部系统时钟。产生内部时钟（112），其是系统时钟的相位和频率调整推导。从该内部时钟（112）产生用于数据处理器（10）内的全局时钟（101）。第二单元（9）接收内部时钟（112）并执行相位调整以提供外设时钟（114）。在保持与全局时钟（101）的相位关系的同时，内部时钟（112）的提供将外围时钟（114）产生的依赖性与全局时钟（101）分离。在一个实施例中，实现本发明，而不需要昂贵地使用多个锁相环。

2. 发明授权

US5295101A Array block level redundancy with steering logic 失效
标题翻译：具有转向逻辑的阵列块级冗余
公开(公告)号：US5295101A
公开(公告)日：1994-03-15
申请号：US829124
申请日：1992-01-31
申请人： Michael C. Stephens, Jr. , Scott E. Smith , Charles J. Pilch , Duy-Loan T. Le , Terry T. Tsai , Arthur R. Piejko
发明人： Michael C. Stephens, Jr. , Scott E. Smith , Charles J. Pilch , Duy-Loan T. Le , Terry T. Tsai , Arthur R. Piejko
IPC分类号： G11C11/401 , G06F11/10 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/81 , G11C29/88 , G06F11/1008
摘要： The described embodiments of the present invention provide a circuit and method for a two level redundancy scheme for a semiconductor memory device. The memory device has one or more data blocks (12) with each data block (12) having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks (14) with each sub-block having a plurality of the memory cells. The first level redundancy scheme includes a few redundant elements for each sub-block for the replacement of defective elements, as is common in many modern semiconductor devices. The second level redundancy scheme includes at least one redundant sub-block of memory cells as part of the main memory for a fully functional memory device or, as an extra level of redundancy for at least one sub-block of memory cells containing defects which are not repairable using the redundant elements. When activated for redundancy, the second level redundancy scheme replaces at least one defective sub-block of memory devices with a like number of redundant sub-blocks of memory devices.
摘要翻译：本发明的所描述的实施例提供了一种用于半导体存储器件的二级冗余方案的电路和方法。存储器件具有一个或多个数据块（12），每个数据块（12）具有沿着行线和列线布置在可寻址行和列中的存储单元阵列。每个阵列被配置成子块（14），每个子块具有多个存储单元。第一级冗余方案包括用于替换缺陷元件的每个子块的少数冗余元件，这在许多现代半导体器件中是常见的。第二级冗余方案包括作为用于全功能存储器件的主存储器的一部分的存储器单元的至少一个冗余子块，或者作为包含缺陷的至少一个存储器单元子块的冗余级别不可修复使用冗余元素。当被激活用于冗余时，第二级冗余方案用存储器设备的相同数目的冗余子块替换至少一个存储器件的有缺陷子块。

3. 发明申请

US20090302885A1 TWO TRANSISTOR TIE CIRCUIT WITH BODY BIASING 审中-公开
标题翻译：具有身体偏转的两个晶体管电路
公开(公告)号：US20090302885A1
公开(公告)日：2009-12-10
申请号：US12134273
申请日：2008-06-06
申请人： JIANAN YANG , Wang K. Chen , Stephen G. Jamison , Arthur R. Piejko , Jun Tang
发明人： JIANAN YANG , Wang K. Chen , Stephen G. Jamison , Arthur R. Piejko , Jun Tang
IPC分类号： H03K19/003 , G05F1/00
CPC分类号： H03K19/003 , H03K2217/0018
摘要： A circuit for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, which is coupled to a first voltage supply, a second current terminal, a control terminal, and a bulk terminal; and (2) an n-type transistor having a first current terminal, which is coupled to a second voltage supply different from the first voltage supply, a second current terminal, a control terminal, and a bulk terminal, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node.
摘要翻译：提供了一种用于车身偏置的电路。电路包括：（1）具有第一电流端子的p型晶体管，其耦合到第一电压源，第二电流端子，控制端子和体积端子; 和（2）具有第一电流端子的n型晶体管，其耦合到不同于第一电压源的第二电压源，第二电流端子，控制端子和体积端子，其中， p型晶体管，p型晶体管的第二电流端子和n型晶体管的控制端子耦合到第一节点，其中p型晶体管的控制端子，n型晶体管的体积端子型晶体管，并且第二晶体管的第二电流端子耦合到不同于第一节点的第二节点。

4. 发明授权

US07187205B2 Integrated circuit storage element having low power data retention and method therefor 有权
标题翻译：具有低功率数据保持的集成电路存储元件及其方法
公开(公告)号：US07187205B2
公开(公告)日：2007-03-06
申请号：US11065793
申请日：2005-02-25
申请人： Ravindraraj Ramaraju , David R. Bearden , Arthur R. Piejko
发明人： Ravindraraj Ramaraju , David R. Bearden , Arthur R. Piejko
IPC分类号： H03K19/0175
CPC分类号： H03K3/356008
摘要： A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a second power supply voltage terminal. The second power supply voltage terminal for receiving a second power supply voltage that is lower than the first power supply voltage. During a normal mode of operation, the second power supply voltage is not provided to the second latch. During a low power mode of operation data is transferred from the first latch to the second latch and the first latch is powered down. The data is retained by the second latch while in low power mode.
摘要翻译：存储元件（10）包括第一闩锁（12）和第二闩锁（14）。第一锁存器（12）耦合到第一电源电压端子，用于接收第一电源电压。第二锁存器（14）耦合到第二电源电压端子。所述第二电源电压端子用于接收低于所述第一电源电压的第二电源电压。在正常操作模式期间，第二电源电压不被提供给第二锁存器。在低功率操作模式期间，数据从第一锁存器传送到第二锁存器，并且第一锁存器掉电。在低功率模式下，数据由第二个锁存器保留。

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