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1. 发明授权

US07081842B2 Electronic component value trimming systems 失效
标题翻译：电子元件修整系统
公开(公告)号：US07081842B2
公开(公告)日：2006-07-25
申请号：US10967756
申请日：2004-10-18
申请人： Hayden Clavie Cranford, Jr. , Louis Lu-Chen Hsu , James Stephen Mason , Gareth John Nicholls , Philip Murfet , Samuel Ray
发明人： Hayden Clavie Cranford, Jr. , Louis Lu-Chen Hsu , James Stephen Mason , Gareth John Nicholls , Philip Murfet , Samuel Ray
IPC分类号： H03M1/10
CPC分类号： H01C17/22
摘要： Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.
摘要翻译：描述了一种用于修整电子部件的值的系统。该系统包括：至少一个修整部件，每个修剪部件具有相关联的开关，用于响应于控制矢量中的对应位选择性地将修剪部件连接到电子部件。如果电子部件的净值和任何连接的修整部件与期望值不同，则包括比较器以产生具有第一值的输出位。连接到开关和比较器的控制器根据比较器的输出产生控制向量，该控制器包括用于顺序地从比较器接收连续输出位的移位寄存器; 其中所述控制向量包括所述移位寄存器的内容，并且其中所述控制矢量中的所述第一值的位影响相应开关的切换。

2. 发明申请

US20050127978A1 Electronic component value trimming systems 失效
标题翻译：电子元件修整系统
公开(公告)号：US20050127978A1
公开(公告)日：2005-06-16
申请号：US10967756
申请日：2004-10-18
申请人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
发明人： Hayden Cranford , Louis Hsu , James Mason , Gareth Nicholls , Philip Murfet , Samuel Ray
IPC分类号： H01C17/22 , H03K3/00
CPC分类号： H01C17/22
摘要： Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.
摘要翻译：描述了一种用于修整电子部件的值的系统。该系统包括：至少一个修整部件，每个修剪部件具有相关联的开关，用于响应于控制矢量中的对应位选择性地将修剪部件连接到电子部件。如果电子部件的净值和任何连接的修整部件与期望值不同，则包括比较器以产生具有第一值的输出位。连接到开关和比较器的控制器根据比较器的输出产生控制向量，该控制器包括用于顺序地从比较器接收连续输出位的移位寄存器; 其中所述控制向量包括所述移位寄存器的内容，并且其中所述控制矢量中的所述第一值的位影响相应开关的切换。

3. 发明申请

US20070279117A1 METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING 审中-公开
标题翻译：高频时钟信号增益的方法与系统
公开(公告)号：US20070279117A1
公开(公告)日：2007-12-06
申请号：US11769408
申请日：2007-06-27
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, providing a clock gating signal with a timing relationship to a clock signal and a differential pair current to a buffer differential pair load element. Switching the differential pair current from the load element to a buffer differential pair responsive to a gating signal pulse, the gating signal pulse correlated to a first clock signal pulse, the buffer differential pair buffers a second clock signal pulse occurring immediately and sequentially after the first clock signal pulse and successive clock signal pulses as a buffer clock signal output, the output comprising a plurality of pulses each having the clock signal amplitude and the clock signal pulse width.
摘要翻译：提供差分时钟信号门控方法和系统，提供具有与时钟信号的时序关系的时钟选通信号和到缓冲器差分对负载元件的差分对电流。响应于门控信号脉冲将差分对电流从负载元件切换到缓冲差分对，门控信号脉冲与第一时钟信号脉冲相关，缓冲差分对缓冲在第一时钟信号脉冲之后立即和顺序发生的第二时钟信号脉冲时钟信号脉冲和连续时钟信号脉冲作为缓冲时钟信号输出，所述输出包括多个脉冲，每个脉冲具有时钟信号幅度和时钟信号脉冲宽度。

4. 发明申请

US20070069793A1 Method and system for high frequency clock signal gating 失效
标题翻译：高频时钟信号门控方法及系统
公开(公告)号：US20070069793A1
公开(公告)日：2007-03-29
申请号：US11235758
申请日：2005-09-27
申请人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
发明人： Hayden Cranford , Stacy Garvin , Vernon Norman , Samuel Ray , Wayne Utter
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.
摘要翻译：提供了一种差分时钟信号门控方法和系统，其中时钟缓冲器电路控制路径产生与时钟信号的定时关系的时钟门控信号。时钟门控信号将响应于第一时钟信号脉冲负半部分的与时钟信号通信的时钟缓冲器电路控制路径上的缓冲器门控。缓冲器提供在第一时钟信号脉冲之后立即和顺序发生的第二和连续时钟信号脉冲，作为输出到第二级时钟路径中的第二缓冲级的缓冲时钟信号，每个具有标称时钟幅度和标称时钟脉冲宽度时钟信号无抖动。

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