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1. 发明申请

US20120273860A1 NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY 有权
标题翻译：非易失性存储器单元具有改进的传感和可靠性
公开(公告)号：US20120273860A1
公开(公告)日：2012-11-01
申请号：US13541755
申请日：2012-07-04
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
IPC分类号： H01L27/06
CPC分类号： H01L27/088 , G11C16/0458 , G11C16/28 , G11C16/3418
摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
摘要翻译：唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。第二耦合电容器的一端连接到第二晶体管的栅极并耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

2. 发明申请

US20120087170A1 Single Polysilicon Non-Volatile Memory 有权
标题翻译：单多晶硅非易失性存储器
公开(公告)号：US20120087170A1
公开(公告)日：2012-04-12
申请号：US12899562
申请日：2010-10-07
申请人： Hau-Yan Lu , Ching-Sung Yang , Shih-Chen Wang , Hsin-Ming Chen
发明人： Hau-Yan Lu , Ching-Sung Yang , Shih-Chen Wang , Hsin-Ming Chen
IPC分类号： G11C17/04 , G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.
摘要翻译：一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。一次可编程存储单元阵列包括多个存储单元。每个存储单元被布置在位线和字线的交点处。电压泵浦电路包括多个局部升压电路。每个本地升压电路由多个存储单元的相应存储单元共享。编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

3. 发明授权

US08363475B2 Non-volatile memory unit cell with improved sensing margin and reliability 有权
标题翻译：非易失性存储单元，具有改进的感测裕度和可靠性
公开(公告)号：US08363475B2
公开(公告)日：2013-01-29
申请号：US12750650
申请日：2010-03-30
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/088 , G11C16/0458 , G11C16/28 , G11C16/3418
摘要： A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
摘要翻译：非易失性存储单元包括第一晶体管对以及第一和第二控制栅极。第一晶体管对包括串联和相同类型的第一和第二晶体管。第一和第二晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极。第一控制栅极通过隧道结耦合到第一浮动多晶硅栅极，并且第二控制栅极通过另一隧道结耦合到第二浮动多晶硅栅极。

4. 发明申请

US20110242893A1 NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY 有权
标题翻译：非易失性存储器单元具有改进的传感和可靠性
公开(公告)号：US20110242893A1
公开(公告)日：2011-10-06
申请号：US12750650
申请日：2010-03-30
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/088 , G11C16/0458 , G11C16/28 , G11C16/3418
摘要： A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.
摘要翻译：非易失性存储单元包括第一晶体管对以及第一和第二控制栅极。第一晶体管对包括串联和相同类型的第一和第二晶体管。第一和第二晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极。第一控制栅极通过隧道结耦合到第一浮动多晶硅栅极，并且第二控制栅极通过另一隧道结耦合到第二浮动多晶硅栅极。

5. 发明授权

US08456916B2 Non-volatile memory unit cell with improved sensing margin and reliability 有权
标题翻译：非易失性存储单元，具有改进的感测裕度和可靠性
公开(公告)号：US08456916B2
公开(公告)日：2013-06-04
申请号：US13541755
申请日：2012-07-04
申请人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
发明人： Hsin-Ming Chen , Shih-Chen Wang , Wen-Hao Ching , Yen-Hsin Lai , Hau-Yan Lu , Ching-Sung Yang
IPC分类号： G11C11/34
CPC分类号： H01L27/088 , G11C16/0458 , G11C16/28 , G11C16/3418
摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.
摘要翻译：唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

6. 发明授权

US08339831B2 Single polysilicon non-volatile memory 有权
标题翻译：单晶硅非易失性存储器
公开(公告)号：US08339831B2
公开(公告)日：2012-12-25
申请号：US12899562
申请日：2010-10-07
申请人： Hau-Yan Lu , Ching-Sung Yang , Shih-Chen Wang , Hsin-Ming Chen
发明人： Hau-Yan Lu , Ching-Sung Yang , Shih-Chen Wang , Hsin-Ming Chen
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.
摘要翻译：一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。一次可编程存储单元阵列包括多个存储单元。每个存储单元被布置在位线和字线的交点处。电压泵浦电路包括多个局部升压电路。每个本地升压电路由多个存储单元的相应存储单元共享。编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

7. 发明申请

US20120314474A1 NON-VOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME 审中-公开
标题翻译：非易失性存储器单元结构及其编程和读取方法
公开(公告)号：US20120314474A1
公开(公告)日：2012-12-13
申请号：US13157295
申请日：2011-06-09
申请人： Hsin-Ming Chen , Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
发明人： Hsin-Ming Chen , Hau-Yan Lu , Shih-Chen Wang , Ching-Sung Yang
IPC分类号： G11C17/18 , H01L27/12
CPC分类号： G11C17/16 , G11C17/18 , H01L21/84 , H01L27/101 , H01L27/1021 , H01L27/1203
摘要： The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A gate is disposed on the first doping region. A gate oxide layer is sandwiched between the first doping region and the gate. A second doping region is disposed within the semiconductor layer and outside the first doping region. A second doping region is in direct contact with the first doping region. A second isolation structure is disposed on the first isolation structure. Further, the second isolation structure surrounds the first doping region and the second doping region. The second isolation structure is also in direct contact with the first doping region and the second doping region.
摘要翻译：本发明提供一种非易失性存储单元结构。第一隔离结构设置在衬底上，半导体层设置在第一隔离结构上以形成绝缘体上硅器件。第一掺杂区域由半导体层的一部分制成。栅极设置在第一掺杂区域上。栅极氧化层夹在第一掺杂区域和栅极之间。第二掺杂区域设置在半导体层内并且在第一掺杂区域的外部。第二掺杂区域与第一掺杂区域直接接触。第二隔离结构设置在第一隔离结构上。此外，第二隔离结构围绕第一掺杂区域和第二掺杂区域。第二隔离结构也与第一掺杂区和第二掺杂区直接接触。

8. 发明授权

US08638589B2 Operating method for non-volatile memory unit 有权
标题翻译：非易失性存储单元的操作方法
公开(公告)号：US08638589B2
公开(公告)日：2014-01-28
申请号：US13366370
申请日：2012-02-06
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： G11C17/00 , G11C17/18 , G11C16/04 , H01L29/788 , H01L29/66 , H01L23/52
CPC分类号： H01L21/28282 , G11C16/10 , H01L27/11206 , H01L27/11568 , H01L29/42344 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.
摘要翻译：提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。存储单元的操作方法包括以下步骤。在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是设置在第二栅极和阱区域之间。

9. 发明申请

US20120134205A1 OPERATING METHOD FOR MEMORY UNIT 有权
标题翻译：存储单元操作方法
公开(公告)号：US20120134205A1
公开(公告)日：2012-05-31
申请号：US13366370
申请日：2012-02-06
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： G11C11/34
CPC分类号： H01L21/28282 , G11C16/10 , H01L27/11206 , H01L27/11568 , H01L29/42344 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.
摘要翻译：提供了一种用于存储单元的操作方法，其中存储单元包括阱区，选择栅极，第一栅极，第二栅极，氧化物氮化物间隔物，第一扩散区域和第二扩散区域。存储单元的操作方法包括以下步骤。在编程操作期间，击穿电压通过形成在选择栅极下方的第一沟道区域耦合到第二扩散区域。编程电压被顺序地或同时地施加到第一栅极和第二栅极以破裂第一氧化物层和第二氧化物层，其中第一氧化物层设置在第一栅极和阱区域之间，第二氧化物层是设置在第二栅极和阱区域之间。

10. 发明授权

US08724363B2 Anti-fuse memory ultilizing a coupling channel and operating method thereof 有权
标题翻译：具有耦合通道的抗熔丝存储器及其操作方法
公开(公告)号：US08724363B2
公开(公告)日：2014-05-13
申请号：US13413626
申请日：2012-03-06
申请人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
发明人： Hau-Yan Lu , Hsin-Ming Chen , Ching-Sung Yang
IPC分类号： G11C17/00
CPC分类号： H01L27/11206 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.
摘要翻译：提供具有耦合通道的反熔丝存储器。反熔丝存储器包括第一导电类型的衬底，第二导电类型的掺杂区域，耦合栅极，栅极介电层，反熔丝栅极和反熔丝层。衬底具有隔离结构。掺杂区域设置在衬底中。在掺杂区域和隔离结构之间限定沟道区域。耦合栅极设置在掺杂区域和隔离结构之间的衬底上。耦合栅极与掺杂区域相邻。栅极电介质层设置在耦合栅极和衬底之间。反熔丝栅极设置在耦合栅极和隔离结构之间的衬底上。反熔丝栅极和耦合栅极之间具有间隔。反熔丝层设置在反熔丝栅极和衬底之间。

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