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1. 发明授权

US07495963B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07495963B2
公开(公告)日：2009-02-24
申请号：US11692501
申请日：2007-03-28
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C2211/5621 , G11C2216/14
摘要： A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile memory cells arranged, memory cells in the main parts serving as information cells used for storing data, the remaining parts as reference cells used for driving a reference current; three or more bit line pairs disposed in the first and second cell arrays, respectively; a sense amplifier so shared by the bit line pairs as to sequentially detect cell current differences between the information cells and the reference cells coupled to the bit line pairs; and first and second data latches arranged to store write data to be written into the first and second cell arrays, each number of the first and second data latches being equal to that of the bit line pairs, which share the sense amplifier and are simultaneously selected.
摘要翻译：半导体存储器件包括：第一和第二单元阵列，每个具有电可重写和非易失性存储单元，主要部分中的存储单元用作用于存储数据的信息单元，其余部分作为用于驱动参考电流的参考单元 ; 分别设置在第一和第二单元阵列中的三个或更多个位线对; 由位线对共享的读出放大器，以顺序地检测信息单元和耦合到位线对的参考单元之间的单元电流差; 以及第一和第二数据锁存器，被布置为存储要写入第一和第二单元阵列的写入数据，每个数量的第一和第二数据锁存器等于共享读出放大器并且被同时选择的位线对的数量。

2. 发明申请

US20070147112A1 SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME 有权
标题翻译：具有相同功能的SENSE放大器和半导体存储器件
公开(公告)号：US20070147112A1
公开(公告)日：2007-06-28
申请号：US11563408
申请日：2006-11-27
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C7/02 , G11C16/06
CPC分类号： G11C7/065 , G11C16/28
摘要： A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.
摘要翻译：读出放大器包括：NMOS晶体管，其漏极耦合到输出节点，其栅极耦合到输出节点，其源极共同耦合到地电位节点; PMOS晶体管，其漏极耦合到NMOS晶体管的漏极，其源极耦合到输入节点; PMOS晶体管，其漏极耦合到输入节点，其栅极耦合到输出节点，其源极经由电流源装置耦合到电源节点; 并且设置在所述输出节点和所述接地电位节点之间的NMOS晶体管将在感测之前导通; 以及设置在输出节点之间的均衡晶体管。

3. 发明授权

US07573744B2 Semiconductor memory device having different capacity areas 失效
标题翻译：具有不同容量区域的半导体存储器件
公开(公告)号：US07573744B2
公开(公告)日：2009-08-11
申请号：US11864089
申请日：2007-09-28
申请人： Toshiaki Edahiro , Toshihiro Suzuki , Haruki Toda
发明人： Toshiaki Edahiro , Toshihiro Suzuki , Haruki Toda
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C2211/5641
摘要： There is provided a semiconductor memory device with NAND strings arranged therein, the NAND string having a plurality of electrically rewritable and non-volatile memory cells connected in series, including: a first data area; and a second data area, which is smaller in capacitance than the first data area and random accessible at a higher rate than the first data area.
摘要翻译：提供了一种其中布置有NAND串的半导体存储器件，该NAND串具有串联连接的多个电可重写和非易失性存储单元，包括：第一数据区; 以及第二数据区域，其电容小于第一数据区域，并且以比第一数据区域更高的速率随机访问。

4. 发明授权

US07495965B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07495965B2
公开(公告)日：2009-02-24
申请号：US11750052
申请日：2007-05-17
申请人： Toshihiro Suzuki , Toshiaki Edahiro , Haruki Toda
发明人： Toshihiro Suzuki , Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/24
摘要： A voltage switching circuit used in a row decoder includes: PMOS transistor P2 and high-voltage NMOS transistor D3 connected in series between VRDEC and TG; PMOS transistor P1 and high-voltage NMOS transistor D2 connected in series between VRDEC and NA; NMOS transistor N2 and high-voltage NMOS transistor D6 connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N1 and high-voltage NMOS transistor D5 connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P1 and P2 are cross-coupled. Gates of D3 and D2 are coupled to TG and NA, respectively.
摘要翻译：在行解码器中使用的电压切换电路包括：串联在VRDEC和TG之间的PMOS晶体管P2和高压NMOS晶体管D3; 串联在VRDEC和NA之间的PMOS晶体管P1和高电压NMOS晶体管D2; 串联在TG和Vss之间的NMOS晶体管N2和高电压NMOS晶体管D6由解码输出Ab驱动; 并且在NA和Vss之间串联连接的NMOS晶体管N1和高电压NMOS晶体管D5由解码输出Aa驱动。 P1和P2的门和排水管交叉耦合。 D3和D2的门分别耦合到TG和NA。

5. 发明申请

US20070268750A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070268750A1
公开(公告)日：2007-11-22
申请号：US11750052
申请日：2007-05-17
申请人： Toshihiro SUZUKI , Toshiaki Edahiro , Haruki Toda
发明人： Toshihiro SUZUKI , Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/24
摘要： A voltage switching circuit used in a row decoder includes: PMOS transistor P2 and high-voltage NMOS transistor D3 connected in series between VRDEC and TG; PMOS transistor P1 and high-voltage NMOS transistor D2 connected in series between VRDEC and NA; NMOS transistor N2 and high-voltage NMOS transistor D6 connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N1 and high-voltage NMOS transistor D5 connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P1 and P2 are cross-coupled. Gates of D3 and D2 are coupled to TG and NA, respectively.
摘要翻译：在行解码器中使用的电压切换电路包括：串联连接在VRDEC和TG之间的PMOS晶体管P 2和高电压NMOS晶体管D 3; 在VRDEC和NA之间串联连接的PMOS晶体管P 1和高电压NMOS晶体管D 2; 串联在TG和Vss之间的NMOS晶体管N 2和高电压NMOS晶体管D 6由解码输出Ab驱动; 并且在NA和Vss之间串联连接的NMOS晶体管N 1和高电压NMOS晶体管D 5由解码输出Aa驱动。 P 1和P 2的闸门和排水沟交叉耦合。 D 3和D 2的门分别耦合到TG和NA。

6. 发明授权

US07522462B2 Sense amplifier and semiconductor memory device with the same 有权
标题翻译：感应放大器和半导体存储器件相同
公开(公告)号：US07522462B2
公开(公告)日：2009-04-21
申请号：US11563408
申请日：2006-11-27
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C16/28
摘要： A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.
摘要翻译：读出放大器包括：NMOS晶体管，其漏极耦合到输出节点，其栅极耦合到输出节点，其源极共同耦合到地电位节点; PMOS晶体管，其漏极耦合到NMOS晶体管的漏极，其源极耦合到输入节点; PMOS晶体管，其漏极耦合到输入节点，其栅极耦合到输出节点，其源极经由电流源装置耦合到电源节点; 并且设置在所述输出节点和所述接地电位节点之间的NMOS晶体管将在感测之前导通; 以及设置在输出节点之间的均衡晶体管。

7. 发明申请

US20070236985A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20070236985A1
公开(公告)日：2007-10-11
申请号：US11692501
申请日：2007-03-28
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C2211/5621 , G11C2216/14
摘要： A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile memory cells arranged, memory cells in the main parts serving as information cells used for storing data, the remaining parts as reference cells used for driving a reference current; three or more bit line pairs disposed in the first and second cell arrays, respectively; a sense amplifier so shared by the bit line pairs as to sequentially detect cell current differences between the information cells and the reference cells coupled to the bit line pairs; and first and second data latches arranged to store write data to be written into the first and second cell arrays, each number of the first and second data latches being equal to that of the bit line pairs, which share the sense amplifier and are simultaneously selected.
摘要翻译：半导体存储器件包括：第一和第二单元阵列，每个具有电可重写和非易失性存储单元，主要部分中的存储单元用作用于存储数据的信息单元，其余部分作为用于驱动参考电流的参考单元 ; 分别设置在第一和第二单元阵列中的三个或更多个位线对; 由位线对共享的读出放大器，以顺序地检测信息单元和耦合到位线对的参考单元之间的单元电流差; 以及第一和第二数据锁存器，被布置为存储要写入第一和第二单元阵列的写入数据，每个数量的第一和第二数据锁存器等于共享读出放大器并且被同时选择的位线对的数量。

8. 发明授权

US07890843B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07890843B2
公开(公告)日：2011-02-15
申请号：US11674342
申请日：2007-02-13
申请人： Haruki Toda , Toshiaki Edahiro
发明人： Haruki Toda , Toshiaki Edahiro
IPC分类号： H03M13/00
CPC分类号： G06F11/1068 , G11C16/0483
摘要： A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circuit includes first and second operation parts for performing addition/subtraction with modulo M and modulo N (where, M and N are integers, which are prime with each other as being obtained by factorizing 2n−1), the first and second operation parts being for performing addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2n−1, and wherein the first and second operation parts each includes an adder circuit.
摘要翻译：存储装置包括具有Galois域GF（2n）上的纠错码的错误检测和校正系统，其具有被配置为以模2n-1执行加法/减法的操作电路，其中所述操作电路包括第一和第二操作部分用于以模M和模N执行加法/减法（其中，M和N是整数，它们通过分解2n-1而获得），第一和第二操作部分用于同时执行加法/减法彼此并联，以模2n-1输出加法/减法的运算结果，并且其中第一和第二操作部分各自包括加法器电路。

9. 发明授权

US08687406B2 Semiconductor memory device and method of controlling the same 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US08687406B2
公开(公告)日：2014-04-01
申请号：US13597740
申请日：2012-08-29
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2213/71 , G11C2213/73
摘要： According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.
摘要翻译：根据实施例，半导体存储器件包括：配置有多个存储单元垫的存储单元阵列，所述存储单元阵列包括多个第一行，第二行和存储单元，并且存储单元阵列被堆叠第一和第二行由每个存储单元垫交替共享; 和外围电路。每个存储单元具有可变电阻特性和电流整流特性。从所有存储器单元的阳极到阴极的取向是相同的。外围电路适用于与所选存储单元的阳极侧连接的选定位线电压的第一线路和第二线路中的一条线路，并且向另一条线路电压施加。

10. 发明申请

US20140009997A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20140009997A1
公开(公告)日：2014-01-09
申请号：US14005149
申请日：2012-03-07
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , H01L27/115
摘要： A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
摘要翻译：一种半导体存储器件，包括存储单元阵列，所述存储单元阵列包括存储单元层，所述存储单元层包含多个用于根据不同电阻状态存储数据的存储单元; 以及访问电路，其操作以访问所述存储单元，所述存储单元在施加第一极性的电压时将所述电阻状态从第一电阻状态改变为第二电阻状态，并且从所述第二电阻状态改变所述电阻状态在施加第二极性的电压的情况下，所述存取电路将访问所述存储单元所需的电压施加到连接到所选择的存储单元的第一和第二行，并且使所述第一和第连接到未选择的存储器单元的第二行进入浮置状态以访问所选存储单元。

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