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1. 发明授权

US06480423B2 High-speed cycle clock-synchronous memory device 失效
标题翻译：高速循环时钟同步存储器件
公开(公告)号：US06480423B2
公开(公告)日：2002-11-12
申请号：US09873313
申请日：2001-06-05
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4087
摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S≧N≧F.
摘要翻译：高速时钟同步存储装置设置有由单元阵列之间和单元阵列之间共享的读出放大器S / A和单元阵列控制器单元CNTRLi，其中与时钟同步的数据/命令的输入和输出访问命令提供所有同时地址数据位（行和列）。通过确认在两个连续命令之间观察到的位的改变，关于配置访问地址的一些地址位，设备判断当前访问是在与先前的访问相同的单元阵列之间，相邻单元阵列之间，还是在远程单元阵列。根据判断，应用适当的命令循环。此时，命令循环满足关系：S> = N> = F。

2. 发明授权

US06295231B1 High-speed cycle clock-synchronous memory device 失效
标题翻译：高速循环时钟同步存储器件
公开(公告)号：US06295231B1
公开(公告)日：2001-09-25
申请号：US09354102
申请日：1999-07-15
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4087
摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between two successive commands, regarding some of address bits configuring access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgement, suitable command cycle is applied. At this time, the command cycle satisfies relationship: S≧N≧F.
摘要翻译：高速时钟同步存储装置设置有由单元阵列之间和单元阵列之间共享的读出放大器S / A和单元阵列控制器单元CNTRLi，其中与时钟同步的数据/命令的输入和输出访问命令提供所有同时地址数据位（行和列）。通过确认在两个连续命令之间观察到的位的变化，关于配置访问地址的一些地址位，设备判断当前访问是在与先前访问相同的单元阵列之间，相邻单元阵列之间还是在远程单元之间阵列根据判断，应用适当的命令循环。此时，命令循环满足关系：S> = N> = F。

3. 发明授权

US06647478B2 Semiconductor memory device 失效
公开(公告)号：US06647478B2
公开(公告)日：2003-11-11
申请号：US10175085
申请日：2002-06-20
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of the read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.

4. 发明授权

US07085881B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07085881B2
公开(公告)日：2006-08-01
申请号：US10681184
申请日：2003-10-09
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F12/02
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between receiving a write command for a write operation in order to write data to the memory cell and the beginning of the write operation is different from a second time between receiving a refresh command for a refresh operation in order to refresh data stored in the memory cell and beginning the write operation.
摘要翻译：半导体存储器件包括位线，耦合到位线的存储单元和耦合到存储器单元的字线。为了向存储器单元写入数据和写入操作的开始，接收写入操作的写入命令之间的第一次不同于接收刷新操作的刷新命令之间的第二次，以刷新存储在存储器单元中的数据存储单元并开始写操作。

5. 发明授权

US06615309B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06615309B2
公开(公告)日：2003-09-02
申请号：US10337977
申请日：2003-01-08
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor memory device. The device includes a bit line, a memory cell coupled to the bit line a word line coupled to the memory cell. A first time between the receiving of a read command for a read operation in order to read data from the memory cell and the beginning of read operation is different from a second time between the receiving of a write command for a write operation in order to write data to the memory cell and the beginning of the write operation.
摘要翻译：半导体存储器件。该设备包括位线，耦合到位线的存储单元，耦合到存储单元的字线。为了从存储单元读取数据和读取操作的开始，读取操作的读取命令的第一次与在写入操作的写入命令的接收之间的第二时间不同，以便写入数据到存储单元和写入操作的开始。

6. 发明授权

US06556507B2 High-speed cycle clock-synchrounous memory device 失效
公开(公告)号：US06556507B2
公开(公告)日：2003-04-29
申请号：US10260341
申请日：2002-10-01
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4087
摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S·N·F.

7. 发明授权

US06484246B2 High-speed random access semiconductor memory device 有权
标题翻译：高速随机存取半导体存储器件
公开(公告)号：US06484246B2
公开(公告)日：2002-11-19
申请号：US09383193
申请日：1999-08-26
申请人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
发明人： Kenji Tsuchida , Haruki Toda , Hitoshi Kuyama
IPC分类号： G06F1202
CPC分类号： G11C7/22 , G11C7/1072 , G11C2207/2281 , G11C2207/229
摘要： A dynamic random access memory device includes a bit line, a memory cell coupled to the bit line, and a word line coupled to the memory cell. A read activation time between receiving a read command for a read operation in order to read data: from the memory cell and activating the word-line-may be different from a write activation time between receiving a write command for a write operation in order to write data to the memory cell and activating the word line.
摘要翻译：动态随机存取存储器件包括位线，耦合到位线的存储单元和耦合到存储器单元的字线。为了从存储器单元读取数据和激活字线，读取操作的读取命令之间的读取激活时间可能不同于接收写入操作的写入命令之间的写入激活时间，以便于将数据写入存储单元并激活字线。

8. 发明授权

US06185150B2 Clock-synchronous system 有权
标题翻译：时钟同步系统
公开(公告)号：US06185150B2
公开(公告)日：2001-02-06
申请号：US09448412
申请日：1999-11-23
申请人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
发明人： Haruki Toda , Kenji Tsuchida , Hitoshi Kuyama
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078
摘要： A delay circuit produces an activation signal by delaying a clock signal by 270 degrees. A receiver circuit is responsive to the activation signal to capture a command latch enable signal indicating a command cycle and produce an internal signal corresponding to the command cycle. An AND circuit produces a command latch signal synchronized with the clock signal during an interval in which the internal signal is produced. Command receivers take command-forming signals only when the command latch signal is applied thereto. That is, these command receivers are activated only when the command latch signal is received but not at all times. This prevents power dissipation from increasing and allows a plurality of signals to be monitored reliably.
摘要翻译：延迟电路通过将时钟信号延迟270度来产生激活信号。接收器电路响应于激活信号以捕获指示命令周期的命令锁存使能信号并产生对应于命令周期的内部信号。 AND电路在产生内部信号的间隔期间产生与时钟信号同步的命令锁存信号。命令接收器只有当命令锁存信号被施加到命令形成信号时才采取命令形成信号。也就是说，这些命令接收器仅在接收到命令锁存信号时才被激活，而不是始终被激活。这防止功率消耗增加，并且允许可靠地监视多个信号。

9. 发明申请

US20050111286A1 Clock-synchronous semiconductor memory device 失效
公开(公告)号：US20050111286A1
公开(公告)日：2005-05-26
申请号：US11023397
申请日：2004-12-29
申请人： Haruki Toda , Hitoshi Kuyama
发明人： Haruki Toda , Hitoshi Kuyama
IPC分类号： G11C7/10 , G11C8/04 , G11C8/00
CPC分类号： G11C8/04 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C11/401 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C2207/2254
摘要： A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

10. 发明授权

US5986968A Clock-synchronous semiconductor memory device and access method thereof 失效
标题翻译：时钟同步半导体存储器件及其访问方法
公开(公告)号：US5986968A
公开(公告)日：1999-11-16
申请号：US113570
申请日：1998-07-10
申请人： Haruki Toda , Hitoshi Kuyama
发明人： Haruki Toda , Hitoshi Kuyama
IPC分类号： G11C7/10 , G11C8/04 , G11C7/00
CPC分类号： G11C8/04 , G11C7/1045 , G11C7/1072
摘要： A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O section is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.
摘要翻译：时钟同步半导体存储器件包括以矩阵形式布置的许多存储器单元，用于对连续的外部供给的基本时钟信号的实际循环次数进行计数的计数部分，用于输入行使能控制信号（/ RE）的控制部分，以及与基本时钟信号不同的外部设备提供的与基本控制信号同步的指令级别的列使能控制信号（/ CE），并且用于设置用于数据访问的初始地址以及用于执行由控制部分设置的地址的数据访问操作的数据I / O部分。在设备中，通过控制部分设置初始地址之后，在计数部分计数了指定数量的基本时钟信号之后，通过数据I / O部分从存储器单元输出数据。

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