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1. 发明授权

US4788473A Plasma generating device with stepped waveguide transition 失效
标题翻译：等离子体发生器件，具有阶梯式波导过渡
公开(公告)号：US4788473A
公开(公告)日：1988-11-29
申请号：US63972
申请日：1987-06-19
申请人： Haruhisa Mori , Motoo Nakano , Yoshinobu Ono , Takashi Igarashi , Masanao Hotta
发明人： Haruhisa Mori , Motoo Nakano , Yoshinobu Ono , Takashi Igarashi , Masanao Hotta
IPC分类号： H01J27/18 , H01J37/08 , H01J37/32 , H01J3/04
CPC分类号： H01J37/32229 , H01J27/18 , H01J37/08
摘要： A plasma generating device comprises:a rectangular wave guide for transmitting microwaves, wherein the width of the plasma generating device is decreased in the direction of an electrical field of the microwaves; a plasma generating chamber wherein plasma is generated by absorbing, in a gas, microwave energy transmitted by the rectangular wave guide, and a part of the plasma generating chamber has a rectangular cross-section taken along the plane perpendicular to the microwave propagation direction. A magnetic field generating device is provided having the same axial direction as the direction of propagation of the microwaves and applies a magnetic field having an Electron Cyclotron Resonance intensity to the plasma generating chamber. The magnetic field generating device is provided at least one location outside of the direction of the microwave electrical field direction, and a dielectric window is provided between the rectangular wave guide and the plasma generating chamber to realize a vacuum seal of the plasma generating chamber.
摘要翻译：一种等离子体产生装置包括：用于传输微波的矩形波导，其中所述等离子体产生装置的宽度在所述微波的电场方向上减小; 等离子体产生室，其中通过在气体中吸收由矩形波导传输的微波能量而产生等离子体，并且等离子体产生室的一部分具有沿着与微波传播方向垂直的平面截取的矩形截面。提供具有与微波传播方向相同轴向的磁场产生装置，并向等离子体产生室施加具有电子回旋共振强度的磁场。磁场产生装置设置在微波电场方向外的至少一个位置处，并且在矩形波导和等离子体发生室之间设置介质窗，以实现等离子体发生室的真空密封。

2. 发明授权

US4258077A Method of ion implantation into a semiconductor substrate provided with an insulating film 失效
标题翻译：离子注入设置有绝缘膜的半导体衬底的方法
公开(公告)号：US4258077A
公开(公告)日：1981-03-24
申请号：US88468
申请日：1979-10-26
申请人： Haruhisa Mori , Motoo Nakano
发明人： Haruhisa Mori , Motoo Nakano
IPC分类号： H01L21/265 , H01L21/266 , C23C17/00
CPC分类号： H01L21/265 , H01L21/266 , Y10S438/91
摘要： In the production of a semiconductor device, such as an IC including MOS transistors, impurity ions are implanted into the semiconductor substrate of the device provided with an insulating film. The insulating film is electrically charged by the impurity ions and may be destroyed due to an electric potential between the insulating film and the semiconductor substrate. A novel process provided by the invention prevents the destruction of the insulating film and shortens the ion implantation time, since the beam current of the impurity ions is successively increased until the required dosing amount is obtained.
摘要翻译：在诸如包括MOS晶体管的IC的半导体器件的制造中，杂质离子注入到设置有绝缘膜的器件的半导体衬底中。绝缘膜由杂质离子带电，并且可能由于绝缘膜和半导体衬底之间的电位而被破坏。由于本发明提供的新颖方法防止了绝缘膜的破坏并缩短了离子注入时间，因为杂质离子的束电流连续增加，直到获得所需的给药量。

3. 发明授权

US4806769A Disk exchangeable target mechanism with effective cooling means, for ion implantation system 失效
标题翻译：具有有效冷却手段的磁盘可更换目标机构，用于离子注入系统
公开(公告)号：US4806769A
公开(公告)日：1989-02-21
申请号：US51397
申请日：1987-05-19
申请人： Haruhisa Mori , Motoo Nakano
发明人： Haruhisa Mori , Motoo Nakano
IPC分类号： H01L21/265 , H01J37/317 , G21K5/08
CPC分类号： H01J37/3171
摘要： An improved disk exchangeable target mechanism for an ion implantation system includes an effective cooling means for preventing thermal damage to a resist and for improving an implantation quality of semiconductor wafers. The target mechanism includes a metal disk on which a semiconductor wafer(s) to be ion-implanted are mounted on a first face thereof, a support including a metal base having the target disk mounted thereon, and a shaft incorporated with the base, and a medium, provided between a second face of the target disk opposite to the first face and the base, for thermally contact therebetween. Preferably, the base of the support is provided with a cavity and the shaft is provided with holes communicating with the cavity, whereby a cooling medium is inserted into the cavity through one hole and is drained from the cavity through another hole. Furthermore, preferably, the target disk is provided with a thermal transportation unit, such as heat pipes, for transporting thermal energy from a portion(s) at which a high temperature is caused by ion implantation energy, to another portion(s) at which the temperature is low.
摘要翻译：用于离子注入系统的改进的盘可更换靶机构包括有效的冷却装置，用于防止对抗蚀剂的热损伤并改善半导体晶片的植入质量。目标机构包括在其第一面上安装有被离子注入的半导体晶片的金属盘，包括安装有目标盘的金属基座的支撑体和与基座结合的轴，以及介质，设置在与第一面相对的目标盘的第二面与基座之间，用于与它们之间的热接触。优选地，支撑件的基部设置有空腔，并且轴设置有与空腔连通的孔，由此冷却介质通过一个孔插入空腔中，并且通过另一个孔从空腔排出。此外，优选地，目标盘设置有热传递单元，例如热管，用于将热能从由离子注入能量引起高温的部分传送到另一部分，其中温度低。

4. 发明授权

US4375993A Method of producing a semiconductor device by simultaneous multiple laser annealing 失效
标题翻译：通过同时进行多次激光退火制造半导体器件的方法
公开(公告)号：US4375993A
公开(公告)日：1983-03-08
申请号：US252216
申请日：1981-04-08
申请人： Haruhisa Mori , Hajime Kamioka , Motoo Nakano , Nobuo Sasaki
发明人： Haruhisa Mori , Hajime Kamioka , Motoo Nakano , Nobuo Sasaki
IPC分类号： H01L29/78 , H01L21/20 , H01L21/208 , H01L21/263 , H01L21/268 , H01L21/321 , H01L21/324 , H01L21/265
CPC分类号： H01L21/321 , H01L21/02488 , H01L21/02532 , H01L21/02683 , H01L21/02686 , H01L21/02691 , H01L21/268 , Y10S148/09 , Y10S148/091 , Y10S148/093 , Y10S148/123
摘要： A method of producing a semiconductor device which comprises steps of forming an insulator layer on a semiconductor substrate, forming a semiconductor layer on the insulator layer and then annealing the semiconductor layer by means of a first laser with a second laser being applied to the insulator layer to heat it while the first layer is applied to the semiconductor laser.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成绝缘体层，在绝缘体层上形成半导体层，然后借助第一激光器对半导体层进行退火，第二激光被施加到绝缘体层以在将第一层施加到半导体激光器时加热它。

5. 发明授权

US5888633A Micro-structures having structural members capable of withstanding permanent bend 失效
标题翻译：具有能够承受永久弯曲的结构构件的微结构
公开(公告)号：US5888633A
公开(公告)日：1999-03-30
申请号：US820359
申请日：1997-03-12
申请人： Motoo Nakano , Hiroshi Nomura , Masaya Katayama , Toshimi Ikeda , Fumihiko Inoue , Junichi Ishikawa , Masahiro Kuwamura
发明人： Motoo Nakano , Hiroshi Nomura , Masaya Katayama , Toshimi Ikeda , Fumihiko Inoue , Junichi Ishikawa , Masahiro Kuwamura
IPC分类号： B81B3/00 , H01L21/02 , H01L21/20 , H01L21/306 , B32B7/02
CPC分类号： B81B3/0005 , B81C1/0092 , H01L21/02063 , H01L28/87 , Y10T428/24744 , Y10T428/24942 , Y10T428/26 , Y10T428/8305
摘要： A micro-structure including at least a first bendable member having first and second ends and being supported at the first end only, and either being spaced from a rigid component, or being spaced from a second bendable member also supported only at a first end thereof. The first member has a length L from the first end to the second end specified by one of the following equations: (a) for the first member adjacent to the rigid component: L
摘要翻译：一种微结构，包括至少第一可弯曲构件，其具有第一端和第二端，仅在第一端处被支撑，并且与刚性构件间隔开，或者与第二可弯曲构件间隔开，第二可弯曲构件也仅在其第一端处支撑。第一构件具有从以下等式之一指定的第一端至第二端的长度L：（a）对于与刚性构件相邻的第一构件：L <（2Edt3 / 3P）+ E，fra 1/4 + EE，其中E是第一构件的材料的杨氏模量; d是第一构件和刚性构件之间的空间的距离; t是第一构件的厚度; 并且P是施加到所述第一构件的外部压力; 或b）对于与第二构件相邻的第一构件：L <（2Ed't3 / 3P）+ E，fra 1/4 + EE，其中E，t和P如上所定义; 并且d'是第一和第二构件之间的空间的距离。

6. 发明授权

US5670885A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5670885A
公开(公告)日：1997-09-23
申请号：US475504
申请日：1995-06-07
申请人： Takashi Iwai , Motoo Nakano
发明人： Takashi Iwai , Motoo Nakano
IPC分类号： H01L27/02 , G01R27/00
CPC分类号： H01L27/0248
摘要： A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).
摘要翻译：半导体器件具有第一导电型半导体衬底（19），包括形成在第二导电型半导体层（20）中的垂直双极晶体管（18）的内部电路和保护元件（14）。保护元件包括形成在设置在半导体衬底（19）上的第二导电型半导体层（20a）的上部的第一导电型扩散层（22a）和第二导电型扩散层（27,30）形成在第一导电型扩散层（22a）中。扩散层（27,30）至少部分地比垂直双极晶体管（18）的发射极扩散层（23）更深。

7. 发明授权

US4541074A Semiconductor device for memory cell 失效
标题翻译：用于存储单元的半导体器件
公开(公告)号：US4541074A
公开(公告)日：1985-09-10
申请号：US393118
申请日：1982-06-28
申请人： Motoo Nakano
发明人： Motoo Nakano
IPC分类号： G11C17/00 , G11C17/12 , H01L21/8229 , H01L21/8246 , H01L27/102 , H01L27/112 , H01L29/78 , G11C11/40
CPC分类号： H01L27/112 , G11C17/12
摘要： A ROM including memory cells having characteristics corresponding to the "1" or "0" information to be stored, the correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of a semiconductor layer in the semiconductor devices of the memory cells.
摘要翻译：包括具有与要存储的“1”或“0”信息对应的特征的存储单元的ROM，通过改变半导体层的至少一部分的导电类型来实现与“1”或“0”信息的对应关系存储单元的半导体器件。

8. 发明授权

US4350536A Method of producing dynamic random-access memory cells 失效
标题翻译：生成动态随机存取存储单元的方法
公开(公告)号：US4350536A
公开(公告)日：1982-09-21
申请号：US180947
申请日：1980-08-25
申请人： Motoo Nakano , Tsutomu Ogawa
发明人： Motoo Nakano , Tsutomu Ogawa
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/78 , H01L21/02 , H01L21/18 , H01L21/22 , H01L21/265
CPC分类号： H01L27/1085 , H01L27/10805
摘要： The invention is concerned with an improved method of producing a one-transistor cell for a dynamic RAM having a capacitor plate, a transfer gate and a shallow n.sup.+ -type region and a deeper p.sup.+ -type region for a junction capacitance. After formation of a thin oxide layer of a dielectric for an MOS capacitance, a patterned photo resist layer is formed. Using the photo resist layer as a mask, n-type impurities are doped into a semiconductor substrate. The capacitor plate and a masking layer are deposited on the photo resist layer and the thin oxide layer. P-type impurities are doped into the capacitor plate. Then, portions of the capacitor plate and masking layer on the photo resist layer are removed by removing the photo resist layer. An end portion of the capacitor plate is removed from under an edge of the remaining masking layer by etching. The p-type impurities are diffused into the silicon substrate by heating to form the deeper p.sup.+ -type region which does not extend beyond the n.sup.+ -type region.
摘要翻译：本发明涉及一种用于动态RAM的单晶体管单元的改进方法，其具有用于结电容的电容器板，传输栅极和浅n +型区域和较深p +型区域。在形成用于MOS电容的电介质的薄氧化物层之后，形成图案化的光致抗蚀剂层。使用光致抗蚀剂层作为掩模，将n型杂质掺杂到半导体衬底中。电容器板和掩模层沉积在光致抗蚀剂层和薄氧化物层上。 P型杂质被掺杂到电容器板中。然后，通过除去光致抗蚀剂层来除去光致抗蚀剂层上的电容器板和掩模层的部分。电容器板的端部通过蚀刻从剩下的掩模层的边缘下方去除。 p型杂质通过加热扩散到硅衬底中以形成不延伸超过n +型区域的较深p +型区域。

9. 发明授权

US4727043A Method of manufacturing a non-volatile memory 失效
标题翻译：制造非易失性存储器的方法
公开(公告)号：US4727043A
公开(公告)日：1988-02-23
申请号：US792238
申请日：1985-10-29
申请人： Takashi Matsumoto , Motoo Nakano
发明人： Takashi Matsumoto , Motoo Nakano
IPC分类号： H01L21/8247 , H01L21/265 , H01L29/788 , H01L29/792 , H01L21/283
CPC分类号： H01L21/2652 , H01L29/7883
摘要： An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through an insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.
摘要翻译：通过本发明的方法提供改进的可电性可变的只读存储器（EAROM），该存储器件包括浮置栅型场效应晶体管，其中浮置栅极的一部分和漏极区的一部分形成于硅衬底重叠。根据该方法，通过该区域上的二氧化硅的绝缘层将杂质原子离子注入到要形成漏极区域的部分的一部分中。此后，去除进行离子注入的绝缘层，并且在旧绝缘层被去除的地方形成新的绝缘层二氧化硅。通过这种方法，制造出良好的薄绝缘膜。由于没有陷阱电荷的陷阱中心的新鲜绝缘层，绝缘层没有中断写入或擦除信息所需的电子流的缺陷。

10. 发明授权

US4538166A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4538166A
公开(公告)日：1985-08-27
申请号：US571639
申请日：1984-01-17
申请人： Motoo Nakano
发明人： Motoo Nakano
IPC分类号： H01L27/10 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/04
CPC分类号： H01L27/10805 , G11C11/404
摘要： A 1-transistor and 1-capacitor type memory cell includes a first capacitor electrode and a field shield electrode which serves as the second capacitor electrode of the memory cell. A high impurity concentration layer is formed just beneath the first electrode of the capacitor of the memory cell and extends to a field region to form a channel stop area. However, the high impurity concentration layer is inhibited from extending to the transistor gate. This arrangement provides so-called 1-transistor and 1-capacitor type memory cells which are highly integrated, have a long persisting time and are resistant to alpha rays.
摘要翻译： 1晶体管和1电容器型存储单元包括用作存储单元的第二电容器电极的第一电容器电极和场屏蔽电极。在存储单元的电容器的第一电极的正下方形成高杂质浓度层，并且延伸到场区域以形成通道停止区域。然而，高杂质浓度层被抑制延伸到晶体管栅极。这种布置提供了高度集成的所谓的1-晶体管和1-电容型存储单元，具有长的持续时间并且耐α射线。

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