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1. 发明申请

US20100178744A1 MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE WHOSE GATE INSULATING FILM CONTAINS Hf AND O 审中-公开
标题翻译：门绝缘膜包含Hf和O的半导体器件的制造方法
公开(公告)号：US20100178744A1
公开(公告)日：2010-07-15
申请号：US12646233
申请日：2009-12-23
申请人： Haruhiko Takahashi , Hiroshi Minakata , Naoyoshi Tamura
发明人： Haruhiko Takahashi , Hiroshi Minakata , Naoyoshi Tamura
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28185 , H01L29/4966
摘要： An insulating film having Hf and O is formed over a semiconductor substrate. A cap film having oxygen and titanium as constituent elements is formed over the insulating film. The insulating film and cap film are thermally treated in a nitrogen gas or noble gas to diffuse titanium in the cap film into the insulating film to form a gate insulating film. A gate electrode film is formed over the gate insulating film.
摘要翻译：在半导体衬底上形成具有Hf和O的绝缘膜。在绝缘膜上形成具有氧和钛作为构成元件的盖膜。绝缘膜和盖膜在氮气或惰性气体中进行热处理，以将帽膜中的钛扩散到绝缘膜中以形成栅极绝缘膜。在栅极绝缘膜上形成栅极电极膜。

2. 发明授权

US08703596B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08703596B2
公开(公告)日：2014-04-22
申请号：US13610529
申请日：2012-09-11
申请人： Naoyoshi Tamura
发明人： Naoyoshi Tamura
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
摘要翻译：半导体器件包括具有沟道区的硅衬底，形成在沟道区上的栅电极，形成在栅电极两侧的硅衬底的表面中的掩埋半导体区，用于施加到硅衬底a的表面在与硅衬底的表面平行的第一方向上的第一应力以及与硅衬底接触的在沟道区和掩埋半导体区之间形成在硅衬底上的应力膜，用于向硅衬底施加第二应力第二方向与第一方向相反。

3. 发明授权

US08278177B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08278177B2
公开(公告)日：2012-10-02
申请号：US13240303
申请日：2011-09-22
申请人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
发明人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.
摘要翻译：在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。在第二SiGe混晶层上形成第三p型SiGe混晶层。从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

4. 发明授权

US08134189B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08134189B2
公开(公告)日：2012-03-13
申请号：US12183676
申请日：2008-07-31
申请人： Naoyoshi Tamura
发明人： Naoyoshi Tamura
IPC分类号： H01L29/76
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7846 , H01L29/7848 , Y10S257/901
摘要： Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.
摘要翻译：旨在提供高度可靠的半导体器件，适当地增加了沟道区域的应力，从而提高载流子注入速率，从而显着提高晶体管特性，并且也适应于近来较窄的沟道宽度及其制造方法，以及其制造方法，在栅电极的侧面上形成由具有可扩展性的应力膜构成的第一侧壁，在第一侧壁上形成由应力小的膜构成的第二侧壁，半导体例如，SiC层被形成为与第一侧壁隔开，同时将第二侧壁放置在其间。

5. 发明申请

US20120040502A1 MANUFACTURE OF SEMICONDUCTOR DEVICE WITH STRESS STRUCTURE 有权
标题翻译：具有应力结构的半导体器件的制造
公开(公告)号：US20120040502A1
公开(公告)日：2012-02-16
申请号：US13283312
申请日：2011-10-27
申请人： Naoyoshi Tamura
发明人： Naoyoshi Tamura
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848 , Y10S438/933
摘要： A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.
摘要翻译：一种制造半导体器件的方法包括以下步骤：（a）通过栅极绝缘膜在硅衬底上形成栅电极; （b）在硅衬底上形成具有不同蚀刻特性的绝缘膜和牺牲膜的叠层，覆盖栅电极，并各向异性地蚀刻层压，以在栅电极和栅极绝缘膜的侧壁上形成侧壁间隔物 ; （c）在侧壁间隔物的两侧将杂质注入到硅衬底中; （d）蚀刻硅衬底和牺牲膜以在硅衬底中形成凹陷，并且将每个侧壁衬垫的横截面形状改变为大致L形; （e）在凹槽中外延生长含Si-Ge的晶体; 和（f）沉积含有应力的绝缘膜，覆盖侧壁间隔物。

6. 发明授权

US08071435B2 Manufacture of semiconductor device with stress structure 有权
标题翻译：具有应力结构的半导体器件制造
公开(公告)号：US08071435B2
公开(公告)日：2011-12-06
申请号：US12606720
申请日：2009-10-27
申请人： Naoyoshi Tamura
发明人： Naoyoshi Tamura
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848 , Y10S438/933
摘要： A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.
摘要翻译：一种制造半导体器件的方法包括以下步骤：（a）通过栅极绝缘膜在硅衬底上形成栅电极; （b）在硅衬底上形成具有不同蚀刻特性的绝缘膜和牺牲膜的叠层，覆盖栅电极，并各向异性地蚀刻层压，以在栅电极和栅极绝缘膜的侧壁上形成侧壁间隔物 ; （c）在侧壁间隔物的两侧将杂质注入到硅衬底中; （d）蚀刻硅衬底和牺牲膜以在硅衬底中形成凹陷，并且将每个侧壁衬垫的横截面形状改变为大致L形; （e）在凹槽中外延生长含Si-Ge的晶体; 和（f）沉积含有应力的绝缘膜，覆盖侧壁间隔物。

7. 发明申请

US20080122007A1 Semiconductor device and fabrication process thereof 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：US20080122007A1
公开(公告)日：2008-05-29
申请号：US11812516
申请日：2007-06-19
申请人： Shinichi Kawai , Takashi Saiki , Naoyoshi Tamura
发明人： Shinichi Kawai , Takashi Saiki , Naoyoshi Tamura
IPC分类号： H01L27/092
CPC分类号： H01L29/4925 , H01L21/28044 , H01L21/823814 , H01L21/823842 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7833 , H01L29/7834
摘要： A semiconductor device includes a first polycrystalline semiconductor gate electrode structure formed in a first device region of a substrate via a gate insulation film and having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, the first polycrystalline gate electrode structure being doped to the second conductivity type, a second polycrystalline semiconductor gate electrode structure formed in a second device region of the substrate via a gate insulation film and having a stacked structure in which a lower polycrystalline semiconductor layer and an upper polycrystalline semiconductor layer are stacked consecutively, the second polycrystalline gate electrode structure being doped to the first conductivity type, a pair of diffusion regions of the second conductivity type formed in the first device region at respective lateral sides of the first polycrystalline semiconductor gate electrode structure, and a pair of diffusion regions of the first conductivity type formed in the second device region at respective lateral sides of the second polycrystalline semiconductor gate electrode structure, wherein, in each of the first and second polycrystalline semiconductor gate electrode structures, the lower polycrystalline semiconductor layer comprises semiconductor crystal grains of a grain diameter smaller than semiconductor crystal grains constituting the upper polycrystalline semiconductor layer, in each of the first and second polycrystalline semiconductor gate electrode structures, the lower polycrystalline semiconductor layer has a dopant concentration level equal to or higher than a dopant concentration level of the upper polycrystalline semiconductor layer.
摘要翻译：一种半导体器件包括：第一多晶半导体栅极电极结构，其经由栅极绝缘膜形成在基板的第一器件区域中，并具有其中下部多晶半导体层和上部多晶半导体层连续堆叠的堆叠结构，第一多晶栅极电极结构被掺杂到第二导电类型，第二多晶半导体栅极电极结构通过栅极绝缘膜形成在衬底的第二器件区域中并且具有堆叠结构，其中下部多晶半导体层和上部多晶半导体层被连续地堆叠，所述第二多晶栅极电极结构被掺杂到所述第一导电类型，所述第二导电类型的一对扩散区形成在所述第一多晶半导体栅极电极的各个侧面的所述第一器件区域中 e结构，以及在所述第二多晶半导体栅电极结构的各个侧面处形成在所述第二器件区域中的所述第一导电类型的一对扩散区域，其中，在所述第一和第二多晶半导体栅电极结构中的每一个中，多晶半导体层包括晶粒直径小于构成上多晶半导体层的半导体晶粒的半导体晶粒，在第一和第二多晶半导体栅电极结构中，下多晶半导体层的掺杂浓度水平等于或等于比上多晶半导体层的掺杂剂浓度水平高。

8. 发明授权

US07361613B2 Semiconductor device, manufacture and evaluation methods for semiconductor device, and process condition evaluation method 有权
标题翻译：半导体器件，半导体器件的制造和评估方法以及工艺条件评估方法
公开(公告)号：US07361613B2
公开(公告)日：2008-04-22
申请号：US11480960
申请日：2006-07-06
申请人： Mitsuaki Hori , Naoyoshi Tamura , Mayumi Shigeno
发明人： Mitsuaki Hori , Naoyoshi Tamura , Mayumi Shigeno
IPC分类号： H01L21/31
CPC分类号： H01L29/518 , H01L21/28202 , H01L21/3144 , H01L21/823462 , H01L29/513 , H01L29/517
摘要： A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ratio of subject nitrogen atoms to a total number of nitrogen atoms in the gate insulating film is 20% or smaller, wherein three bonds of each subject nitrogen atom are all coupled to silicon atoms and remaining three bonds of each of three silicon atoms connected to the subject nitrogen atom are all coupled to other nitrogen atoms.
摘要翻译：由半导体衬底的部分表面区域设置由氮氧化硅制成的栅极绝缘膜。栅电极设置在栅极绝缘膜上。源极和漏极区域设置在栅电极的两侧。目标氮原子与栅极绝缘膜中氮原子总数的存在比例为20％以下，其中，每个受试氮原子的三个键都与硅原子相连，并且三个硅原子中的每一个的三个键连接到目标氮原子都与其它氮原子偶联。

9. 发明申请

US20080087923A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080087923A1
公开(公告)日：2008-04-17
申请号：US11652131
申请日：2007-01-11
申请人： Naoyoshi Tamura
发明人： Naoyoshi Tamura
IPC分类号： H01L29/94 , H01L21/335
CPC分类号： H01L21/823807 , H01L29/045 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.
摘要翻译：一种半导体器件及其制造方法，其能够使用廉价的结构来提高MOSFET的工作速度。该方法包括以下步骤：形成应力膜以覆盖MOSFET的源极，漏极，侧壁绝缘层和栅极，并在应力膜中形成从应力膜表面向侧壁绝缘层延伸的狭缝。结果，通过狭缝抑制了通过栅极上的应力膜中的局部应力分量使源极和漏极上的应力膜中的局部应力分量被松弛的效果。

10. 发明申请

US20060252280A1 Semiconductor device, manufacture and evaluation methods for semiconductor device, and process condition evaluation method 有权
标题翻译：半导体器件，半导体器件的制造和评估方法以及工艺条件评估方法
公开(公告)号：US20060252280A1
公开(公告)日：2006-11-09
申请号：US11480960
申请日：2006-07-06
申请人： Mitsuaki Hori , Naoyoshi Tamura , Mayumi Shigeno
发明人： Mitsuaki Hori , Naoyoshi Tamura , Mayumi Shigeno
IPC分类号： H01L21/31
CPC分类号： H01L29/518 , H01L21/28202 , H01L21/3144 , H01L21/823462 , H01L29/513 , H01L29/517
摘要： A gate insulating film made of silicon oxynitride is disposed on the partial surface area of a semiconductor substrate. A gate electrode is disposed on the gate insulating film. Source and drain regions are disposed on both sides of the gate electrode. An existence ratio of subject nitrogen atoms to a total number of nitrogen atoms in the gate insulating film is 20% or smaller, wherein three bonds of each subject nitrogen atom are all coupled to silicon atoms and remaining three bonds of each of three silicon atoms connected to the subject nitrogen atom are all coupled to other nitrogen atoms.
摘要翻译：由半导体衬底的部分表面区域设置由氮氧化硅制成的栅极绝缘膜。栅电极设置在栅极绝缘膜上。源极和漏极区域设置在栅电极的两侧。目标氮原子与栅极绝缘膜中氮原子总数的存在比例为20％以下，其中，每个受试氮原子的三个键都与硅原子相连，并且三个硅原子中的每一个的三个键连接到目标氮原子都与其它氮原子偶联。

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