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1. 发明授权

US06629232B1 Copied register files for data processors having many execution units 失效
标题翻译：具有多个执行单位的数据处理器的复制寄存器文件
公开(公告)号：US06629232B1
公开(公告)日：2003-09-30
申请号：US09609911
申请日：2000-07-03
申请人： Ken Arora , Harshvardhan Sharangpani , Rajiv Gupta
发明人： Ken Arora , Harshvardhan Sharangpani , Rajiv Gupta
IPC分类号： G06F1300
CPC分类号： G06F9/3012 , G06F9/30141 , G06F9/3885 , G06F9/3891
摘要： Interconnect-dominated large register files are reduced in chip area and delay time. A register file in a processor having a number of execution units is divided into multiple copies. Different groups of execution units can read from and write to their own copy of the file registers by a set of local read and write ports. All of the register-file copies are synchronized by writing data from the execution units to remote write ports in at least some registers in other copies of the register file. Each copy can be divided into local and global registers. While all copies of the global registers continue to be written by the remote write ports, the local registers can be written only by a local cluster of execution units. Alternatively or additionally, all of the execution units can write to their local register-file copy, but only some of the units can write the global registers in all copies of the register file.
摘要翻译：互连主导的大型寄存器文件在芯片面积和延迟时间上都有所减少。具有多个执行单元的处理器中的寄存器文件被分成多个副本。不同的执行单元组可以通过一组本地读写端口读取和写入其自己的文件寄存器副本。所有寄存器文件副本都通过将数据从执行单元写入到寄存器文件的其他副本的至少一些寄存器中的远程写入端口来同步。每个副本可分为本地和全局寄存器。虽然全局寄存器的所有副本仍然由远程写入端口写入，但本地寄存器只能由本地执行单元集群写入。或者或另外，所有执行单元都可以写入其本地寄存器文件副本，但只有一些单元可以将全局寄存器写入寄存器文件的所有副本。

2. 发明授权

US06625693B2 Fast exception processing 有权
标题翻译：使用多个缓存处理程序进行快速异常处理
公开(公告)号：US06625693B2
公开(公告)日：2003-09-23
申请号：US09304372
申请日：1999-05-04
申请人： Ken Arora , Harshvardhan Sharangpani , Gary Hammond
发明人： Ken Arora , Harshvardhan Sharangpani , Gary Hammond
IPC分类号： G06F1200
CPC分类号： G06F9/3861
摘要： Fast exception processing is disclosed. In one embodiment, a system includes a splice cache, an exception logic, and an instrumentation mechanism. The splice cache contains one or more lightweight handlers. The exception logic is coupled to the splice cache and determines whether the corresponding lightweight handler for an exception is located in the splice cache. The instrumentation mechanism is coupled to the splice cache. The instrumentation mechanism inserts the lightweight handler into an execution stream.
摘要翻译：公开了快速异常处理。在一个实施例中，系统包括拼接高速缓存，异常逻辑和检测机制。拼接缓存包含一个或多个轻量级处理程序。异常逻辑耦合到拼接缓存，并确定对应于异常的轻量级处理程序是否位于拼接缓存中。仪器机制耦合到拼接缓存。仪器化机制将轻量级处理程序插入到执行流中。

3. 发明授权

US06591359B1 Speculative renaming of data-processor registers 有权
标题翻译：将虚拟寄存器规范映射到流水线处理器中的物理寄存器
公开(公告)号：US06591359B1
公开(公告)日：2003-07-08
申请号：US09223843
申请日：1998-12-31
申请人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
发明人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
IPC分类号： G06F934
CPC分类号： G06F9/3863 , G06F9/384 , G06F9/3842
摘要： A pipelined data processor has instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical registers for speculative use by the instruction at a later pipeline stage. The registers have multiple differently translated regions. Failure of speculative renaming reverts to an archive copy of renaming data.
摘要翻译：流水线数据处理器具有不同执行阶段的指令。一些指令将虚拟地址指定为具有物理地址的寄存器的文件。推测翻译器将一个流水线阶段的指令的虚拟寄存器映射到物理寄存器，以便在稍后的流水线阶段由指令进行投机使用。寄存器有多个不同的翻译区域。投机重命名失败恢复到重命名数据的归档副本。

4. 发明授权

US06378063B2 Method and apparatus for efficiently routing dependent instructions to clustered execution units 有权
标题翻译：用于有效地将依赖指令路由到集群执行单元的方法和装置
公开(公告)号：US06378063B2
公开(公告)日：2002-04-23
申请号：US09220154
申请日：1998-12-23
申请人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
发明人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.
摘要翻译：与链亲和单元和周期内依赖性分析仪组合的分散单元在微处理器中路由指令以提高微处理器性能。分散单元响应于存储在链亲和单元中的信息将指令路由到微处理器中的特定簇。循环内依赖性分析器识别到分散单元的指令组的依赖性，并且分散单元基于这些依赖性来路由组中的指令。

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