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1. 发明授权

US06352896B1 Method of manufacturing DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US06352896B1
公开(公告)日：2002-03-05
申请号：US09618597
申请日：2000-07-17
申请人： Haochieh Liu , Hsi-Chuan Chen , Jung-Ho Chang , Hong-Hsiang Tsai , Li-Ming Wang , Sen-Huan Huang , Bor-Ru Sheu , Wen-Kuei Hsieh
发明人： Haochieh Liu , Hsi-Chuan Chen , Jung-Ho Chang , Hong-Hsiang Tsai , Li-Ming Wang , Sen-Huan Huang , Bor-Ru Sheu , Wen-Kuei Hsieh
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814 , H01L27/10885 , H01L27/10888
摘要： A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.
摘要翻译：制造DRAM电容器的方法。在衬底上形成有源区。在基板上方形成多条平行字线。第一插头和第二插头分别形成在用于形成所需位线接触和节点接触的位置之间的字线之间。绝缘材料沉积在字线之间的剩余空间中。在第一插头上形成位线接触。在衬底上形成多个并行位线。位线垂直于字线。位线通过位线接触和第一插头与衬底电连接。位线彼此电绝缘。此外，每个位线由硬材料层覆盖在顶部。最后，在第二插头上形成节点接触。

2. 发明授权

US06291355B1 Method of fabricating a self-aligned contact opening 有权
标题翻译：制造自对准接触开口的方法
公开(公告)号：US06291355B1
公开(公告)日：2001-09-18
申请号：US09404498
申请日：1999-09-23
申请人： Haochieh Liu , Bor-Ru Sheu , Hsi-Chuan Chen , Sen-Huan Huang
发明人： Haochieh Liu , Bor-Ru Sheu , Hsi-Chuan Chen , Sen-Huan Huang
IPC分类号： H01L213065
CPC分类号： H01L21/76897 , H01L2924/0002 , H01L2924/00
摘要： A fabrication method for a self-aligned contact opening involves using polysilicon to protect a cap layer above a conductive line or even a corner of a spacer on a sidewall of the conductive line. A silicon oxide layer is then etched using a conventional silicon oxide etching recipe to form a self-aligned contact opening. This conventional silicon oxide etching recipe not only has a higher etching selectivity for silicon oxide to silicon nitride, but also yields a higher etching selectivity ratio for silicon oxide to polysilicon.
摘要翻译：用于自对准接触开口的制造方法包括使用多晶硅来保护导电线上方的帽层或甚至导电线侧壁上的间隔物的角部。然后使用常规氧化硅蚀刻配方蚀刻氧化硅层，以形成自对准的接触开口。这种常规的氧化硅蚀刻配方不仅对于氧化硅对氮化硅具有更高的蚀刻选择性，而且对于氧化硅到多晶硅也产生更高的蚀刻选择性比。

3. 发明授权

US06882002B2 Non-volatile semiconductor memory device having a dielectric layer formed around and planar with a first stack's top surface 有权
标题翻译：具有在第一堆叠顶表面周围形成和平坦的介电层的非易失性半导体存储器件
公开(公告)号：US06882002B2
公开(公告)日：2005-04-19
申请号：US10397632
申请日：2003-03-25
申请人： Bor-Ru Sheu
发明人： Bor-Ru Sheu
IPC分类号： H01L21/306 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/72
CPC分类号： H01L27/11521 , H01L27/115
摘要： The structure and manufacturing method of a non-volatile semiconductor memory device are provided. The method for manufacturing a cell stack includes steps of: (a) providing a substrate; (b) forming on the substrate an oxide layer, a first conductive layer, a first dielectric layer, and a second conductive layer sequentially; (c) etching back to form a first recess pattern; (d) filling with a second dielectric layer; (e) depositing a third dielectric layer; (f) depositing a fourth dielectric layer; (g) etching to form a second recess pattern; (h) depositing a barrier layer on the second recess pattern; and (i) filling with a third conductive layer. The proposed structure of a cell stack includes a substrate, an oxide layer, a first stack, a second dielectric layer, a second stack, a third dielectric layer, and a fourth dielectric layer.
摘要翻译：提供了一种非易失性半导体存储器件的结构和制造方法。制造电池堆的方法包括以下步骤：（a）提供衬底; （b）在基板上依次形成氧化物层，第一导电层，第一介电层和第二导电层; （c）蚀回以形成第一凹槽图案; （d）填充第二电介质层; （e）沉积第三介电层; （f）沉积第四电介质层; （g）蚀刻以形成第二凹槽图案; （h）在第二凹槽图案上沉积阻挡层; 和（i）填充第三导电层。所提出的电池堆结构包括衬底，氧化物层，第一堆叠，第二电介质层，第二堆叠，第三电介质层和第四电介质层。

4. 发明授权

US06764863B2 Memory-storage node and the method of fabricating the same 有权
标题翻译：存储器节点及其制造方法
公开(公告)号：US06764863B2
公开(公告)日：2004-07-20
申请号：US10387476
申请日：2003-03-14
申请人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.
摘要翻译：本发明的存储器存储节点包括半导体衬底，衬底上的第一绝缘层，形成在第一绝缘层内的导电层，以及形成在导电层上的阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。存储器存储节点还包括位于阻挡层上的第一电极，位于第一电极上的电介质层，以及介电层上的第二电极。本发明的存储器存储器的制造方法提供半导体衬底，并在衬底上形成第一绝缘层。在第一绝缘层中形成第一开口，并且在第一开口中设置导电层。然后在第一开口中和导电层上方形成阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。在第一绝缘层和阻挡层之上形成第二绝缘层。在第二绝缘层中形成第二开口以暴露下面的阻挡层的一部分。第一电极形成在第二开口中，并且在第二绝缘层和第一电极上形成电介质层。最后，在电介质层上形成第二电极。

5. 发明授权

US06776622B2 Conductive contact structure and process for producing the same 有权
标题翻译：导电接触结构及其制造方法
公开(公告)号：US06776622B2
公开(公告)日：2004-08-17
申请号：US10205449
申请日：2002-07-26
申请人： Shih-Hsien Yang , Yueh-Cheng Chuang , Bor-Ru Sheu
发明人： Shih-Hsien Yang , Yueh-Cheng Chuang , Bor-Ru Sheu
IPC分类号： H05K100
CPC分类号： H01L21/76877 , H01L21/76895 , H01L23/53238 , H01L24/03 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/14 , H01L2924/19041
摘要： A conductive contact structure to electrically connect to a source/drain region in a semiconductor substrate and a process of making the same. An inlay opening including a pad opening and a bottom opening is formed in the dielectric layer on the semiconductor substrate. The pad opening is larger than and located upon the bottom opening that exposes the source/drain region. The bottom opening and pad opening are sequentially filled with a polysilicon layer and a tungsten layer to form a bottom plug and a metal pad layer, respectively.
摘要翻译：电连接到半导体衬底中的源极/漏极区域的导电接触结构及其制造方法。在半导体衬底上的电介质层中形成包括衬垫开口和底部开口的镶嵌开口。焊盘开口大于并位于露出源极/漏极区域的底部开口上。底部开口和衬垫开口依次填充有多晶硅层和钨层，分别形成底部塞子和金属垫层。

6. 发明授权

US06762482B2 Memory device with composite contact plug and method for manufacturing the same 有权
标题翻译：具有复合触点插头的存储器件及其制造方法
公开(公告)号：US06762482B2
公开(公告)日：2004-07-13
申请号：US10336956
申请日：2003-01-06
申请人： Wen-Chung Liu , Bor-Ru Sheu , Yoshiaki Fukuzumi
发明人： Wen-Chung Liu , Bor-Ru Sheu , Yoshiaki Fukuzumi
IPC分类号： H01L2993
CPC分类号： H01L21/7687 , H01L21/3212 , H01L21/76828 , H01L21/76832 , H01L21/76834 , H01L21/76877 , H01L28/60 , H01L28/90
摘要： A memory device with composite contact plug and method for manufacturing the same. The composite contact plug comprises a first insulating layer deposited on a semiconductor substrate. A contact hole is formed to penetrate through the first insulation layer. A barrier layer is deposited in the contact hole and fills a portion of the contact hole. A contact plug is formed on the barrier layer and fills the contact hole. The first insulating layer is etched back until the surface of the first insulating layer is below the contact plug. A diffusion barrier layer is then deposited on the first insulating layer and the contact plug. The diffusion barrier layer is planarized until the contact plug is exposed to form a composite contact plug. The memory device is constructed on the composite contact plug.
摘要翻译：具有复合接触插头的记忆装置及其制造方法。复合接触插塞包括沉积在半导体衬底上的第一绝缘层。形成穿过第一绝缘层的接触孔。阻挡层沉积在接触孔中并填充接触孔的一部分。接触塞形成在阻挡层上并填充接触孔。第一绝缘层被回蚀刻直到第一绝缘层的表面在接触插塞之下。然后在第一绝缘层和接触插塞上沉积扩散阻挡层。扩散阻挡层被平坦化，直到接触塞被暴露以形成复合接触塞。存储器件构造在复合接触插头上。

7. 发明授权

US06828219B2 Stacked spacer structure and process 有权
标题翻译：堆叠间隔结构和工艺
公开(公告)号：US06828219B2
公开(公告)日：2004-12-07
申请号：US10102742
申请日：2002-03-22
申请人： Shih-Hsien Yang , Yueh-Cheng Chuang , Bor-Ru Sheu
发明人： Shih-Hsien Yang , Yueh-Cheng Chuang , Bor-Ru Sheu
IPC分类号： H01L213205
CPC分类号： H01L29/6656 , H01L21/31116 , H01L21/31612 , H01L21/3185 , H01L21/76897 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10891 , H01L29/41766 , H01L29/66636
摘要： A stacked spacer structure and process adapted for a stacked layer on a semiconductor substrate is described. The stacked spacer structure is formed on the sidewalls of the stacked layer which comprise a conductive layer and a cap layer thereon. A dielectric layer made of a material with low dielectric constant lower than that of silicon nitride is formed on the semiconductor substrate. A first silicon nitride layer is then formed over the substrate. The first silicon nitride layer and dielectric layer are etched sequentially to form an inner spacer on the sidewalls of the stacked layer. A second silicon nitride layer is formed over the substrate and is etched to form an outer spacer on the sidewalls of the inner spacer. By forming the stacked spacer structure of the present invention embedded in low dielectric material, the coupling capacitance produced therein will be greatly reduced.
摘要翻译：描述了适用于半导体衬底上的堆叠层的层叠间隔结构和工艺。层叠的间隔结构形成在层叠层的侧壁上，其中包括导电层和覆盖层。在半导体衬底上形成由低介电常数低于氮化硅的材料制成的电介质层。然后在衬底上形成第一氮化硅层。依次蚀刻第一氮化硅层和电介质层，以在堆叠层的侧壁上形成内部间隔物。在衬底上形成第二氮化硅层，并且被蚀刻以在内衬垫的侧壁上形成外间隔件。通过形成嵌入在低介电材料中的本发明的层叠间隔结构，其中产生的耦合电容将大大降低。

8. 发明授权

US06248643B1 Method of fabricating a self-aligned contact 有权
标题翻译：制造自对准接触的方法
公开(公告)号：US06248643B1
公开(公告)日：2001-06-19
申请号：US09285534
申请日：1999-04-02
申请人： Chien-Sheng Hsieh , Wei-Ray Lin , Fu-Liang Yang , Erik S. Jeng , Bor-Ru Sheu
发明人： Chien-Sheng Hsieh , Wei-Ray Lin , Fu-Liang Yang , Erik S. Jeng , Bor-Ru Sheu
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/32053 , H01L21/76224 , H01L21/76879 , H01L21/76885
摘要： A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, a dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.
摘要翻译：一种使用升高的沟槽隔离，选择性接触插塞沉积和平面化从器件级开始制造自对准触点的方法。该工艺开始于在硅衬底上依次形成栅氧化层和第一栅电极层。接下来，使用牺牲氧化物和氮化物层和选择性蚀刻形成完全平坦化的沟槽隔离区域。形成牺牲衬垫氧化物层和第一牺牲氮化物层。图案化第一牺牲氮化物层，牺牲焊盘氧化物层，第一栅极电极层，栅极氧化物层和硅衬底以形成沟槽。填充氧化物层沉积在沟槽中并在第一牺牲氮化物层上方。执行氧化物蚀刻，其将沟槽中的填充氧化物层的凹陷低于第一氮化物层的顶部的水平面。第二牺牲氮化物层形成在填充氧化物层上并在第一牺牲氮化物层上方。进行化学机械抛光。执行连续氧化物蚀刻，氮化物蚀刻和氧化物蚀刻步骤，定义与第一栅极电极层完全平坦化的升高的沟槽隔离区域。形成硅化物层，电介质层和顶部氮化物层。在顶部氮化物层，电介质层，硅化物层，第一栅极电极层和栅极氧化物层之间，在升高的沟槽隔离区域和升高的沟槽隔离区域上的导电线之间构图形成栅极结构。隔板形成在栅极结构，导电线和升高的沟槽隔离区的侧壁上。然后，在间隔物附近形成自对准的接触塞。

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