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1. 发明授权

US06563161B2 Memory-storage node and the method of fabricating the same 有权
公开(公告)号：US06563161B2
公开(公告)日：2003-05-13
申请号：US09813993
申请日：2001-03-22
申请人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L27108
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.

2. 发明授权

US06764863B2 Memory-storage node and the method of fabricating the same 有权
标题翻译：存储器节点及其制造方法
公开(公告)号：US06764863B2
公开(公告)日：2004-07-20
申请号：US10387476
申请日：2003-03-14
申请人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
发明人： Bor-Ru Sheu , Ming-Chung Chiang , Chung-Ming Chu , Min-Chieh Yang
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/76897 , H01L27/10855 , H01L28/75 , H01L28/90
摘要： The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.
摘要翻译：本发明的存储器存储节点包括半导体衬底，衬底上的第一绝缘层，形成在第一绝缘层内的导电层，以及形成在导电层上的阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。存储器存储节点还包括位于阻挡层上的第一电极，位于第一电极上的电介质层，以及介电层上的第二电极。本发明的存储器存储器的制造方法提供半导体衬底，并在衬底上形成第一绝缘层。在第一绝缘层中形成第一开口，并且在第一开口中设置导电层。然后在第一开口中和导电层上方形成阻挡层。阻挡层优选含有钌基材料，与导电层导电耦合。在第一绝缘层和阻挡层之上形成第二绝缘层。在第二绝缘层中形成第二开口以暴露下面的阻挡层的一部分。第一电极形成在第二开口中，并且在第二绝缘层和第一电极上形成电介质层。最后，在电介质层上形成第二电极。

3. 发明授权

US06368910B1 Method of fabricating ruthenium-based contact plug for memory devices 有权
标题翻译：制造用于存储器件的钌基接触插塞的方法
公开(公告)号：US06368910B1
公开(公告)日：2002-04-09
申请号：US09721796
申请日：2000-11-24
申请人： Bor-Bu Sheu , Chung-Ming Chu , Ming-Chung Chiang , Min-Chieh Yang , Wen-Chung Liu , Jong-Bor Wang , Pai-Hsuan Sun
发明人： Bor-Bu Sheu , Chung-Ming Chu , Ming-Chung Chiang , Min-Chieh Yang , Wen-Chung Liu , Jong-Bor Wang , Pai-Hsuan Sun
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/76877 , H01L23/485 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.
摘要翻译：一种用于制造诸如动态随机存取存储器（DRAM）和铁电随机存取存储器（FRAM）的半导体存储器单元的方法，其具有改善的电容器电极和下面的器件区域之间的接触。它包括以下主要步骤：（1）在晶片表面上形成第一电介质层; （2）在所述第一电介质层中形成至少一个通孔; （3）在通孔中形成钌基塞; 和（4）形成与钌基塞接触的电容器。钌基塞可以由钌金属，导电氧化钌或导电氧化钌和金属钌的叠层制成。该方法允许在不需要屏蔽的情况下制造存储单元，这是在制造过程中保护存储电极不与Si原子反应所需要的。

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