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1. 发明授权

US07230270B2 Self-aligned double gate device and method for forming same 有权
标题翻译：自对准双门装置及其形成方法
公开(公告)号：US07230270B2
公开(公告)日：2007-06-12
申请号：US10997446
申请日：2004-11-24
申请人： Hao-Yu Chen , Ju-Wang Hsu , Baw-Ching Perng , Fu-Liang Yang
发明人： Hao-Yu Chen , Ju-Wang Hsu , Baw-Ching Perng , Fu-Liang Yang
IPC分类号： H01L29/10 , H01L27/01
CPC分类号： H01L29/78648 , H01L27/1203
摘要： In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over the pad layer. A first trench is formed extending through the pad layer, second substrate, buried insulating layer and into the first substrate. The first trench is filled with a first isolation. A second trench is formed in the first isolation and filled with a conductive material. An MOS transistor is formed on the second substrate. A bottom gate is formed under the buried insulating layer and self-aligned to the top gate formed on the second substrate.
摘要翻译：在形成双栅极器件的方法中，在第一衬底上形成厚度小于约30nm的掩埋绝缘层。第二衬底形成在掩埋绝缘层上。衬垫层形成在第二衬底上。掩模层形成在焊盘层上。第一沟槽形成为延伸穿过衬垫层，第二衬底，埋入绝缘层并进入第一衬底。第一个沟槽充满了第一个隔离。在第一隔离中形成第二沟槽并填充导电材料。在第二基板上形成MOS晶体管。底栅形成在掩埋绝缘层的下方，并与形成在第二基板上的顶栅自对准。

2. 发明申请

US20060108644A1 Self-aligned double gate device and method for forming same 有权
标题翻译：自对准双门装置及其形成方法
公开(公告)号：US20060108644A1
公开(公告)日：2006-05-25
申请号：US10997446
申请日：2004-11-24
申请人： Hao-Yu Chen , Ju-Wang Hsu , Baw-Ching Perng , Fu-Liang Yang
发明人： Hao-Yu Chen , Ju-Wang Hsu , Baw-Ching Perng , Fu-Liang Yang
IPC分类号： H01L29/15
CPC分类号： H01L29/78648 , H01L27/1203
摘要： In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over the pad layer. A first trench is formed extending through the pad layer, second substrate, buried insulating layer and into the first substrate. The first trench is filled with a first isolation. A second trench is formed in the first isolation and filled with a conductive material. An MOS transistor is formed on the second substrate. A bottom gate is formed under the buried insulating layer and self-aligned to the top gate formed on the second substrate.
摘要翻译：在形成双栅极器件的方法中，在第一衬底上形成厚度小于约30nm的掩埋绝缘层。第二衬底形成在掩埋绝缘层上。衬垫层形成在第二衬底上。掩模层形成在焊盘层上。第一沟槽形成为延伸穿过衬垫层，第二衬底，埋入绝缘层并进入第一衬底。第一个沟槽充满了第一个隔离。在第一隔离中形成第二沟槽并填充导电材料。在第二基板上形成MOS晶体管。底栅形成在掩埋绝缘层的下方，并与形成在第二基板上的顶栅自对准。

3. 发明授权

US06498067B1 Integrated approach for controlling top dielectric loss during spacer etching 有权
标题翻译：在间隔蚀刻期间控制顶部介电损耗的集成方法
公开(公告)号：US06498067B1
公开(公告)日：2002-12-24
申请号：US10139021
申请日：2002-05-02
申请人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
发明人： Baw-Ching Perng , Ming-Huang Tsai , Ju-Wang Hsu , Hun-Jan Tao
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L29/6656
摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.
摘要翻译：已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物间隔

4. 发明申请

US20070235823A1 CMOS devices with improved gap-filling 有权
标题翻译：具有改进间隙填充的CMOS器件
公开(公告)号：US20070235823A1
公开(公告)日：2007-10-11
申请号：US11393369
申请日：2006-03-30
申请人： Ju-Wang Hsu , Chih-Hsin Ko , Jyu-Horng Shieh , Baw-Ching Perng , Syun-Ming Jang
发明人： Ju-Wang Hsu , Chih-Hsin Ko , Jyu-Horng Shieh , Baw-Ching Perng , Syun-Ming Jang
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843 , Y10S438/981
摘要： A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.
摘要翻译：半导体结构包括衬底和在衬底的第一区域上的第一MOS器件，其中第一MOS器件包括第一间隔衬垫。半导体结构还包括在第二区域上的第二MOS器件，其中第二MOS器件包括第二间隔衬垫。在第一MOS器件上形成具有第一厚度的第一应力膜，并直接在第一间隔衬垫上。在第二MOS器件上形成具有第二厚度的第二应力膜，并且直接在第二间隔衬垫上。第一和第二应力膜可以由相同的材料形成。

5. 发明授权

US06838381B2 Methods for improving sheet resistance of silicide layer after removal of etch stop layer 失效
标题翻译：去除蚀刻停止层之后提高硅化物层的薄层电阻的方法
公开(公告)号：US06838381B2
公开(公告)日：2005-01-04
申请号：US10329598
申请日：2002-12-26
申请人： Peng-Fu Hsu , Ming-Huan Tsai , Baw-Ching Perng , Ju-Wang Hsu , Yaun-Hung Chiu
发明人： Peng-Fu Hsu , Ming-Huan Tsai , Baw-Ching Perng , Ju-Wang Hsu , Yaun-Hung Chiu
IPC分类号： H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/76802 , H01L21/76814 , H01L21/76829
摘要： A method of manufacturing a semiconductor device is provided. A nickel silicide layer (e.g., NiSi) is formed on a substrate. Next, a hydrogen plasma treatment may be performed on the silicide layer, which may induce the formation of metal/silicon hydride bonds in the silicide layer. An etch stop layer is formed over the silicide layer. A dielectric layer is formed over the etch stop layer. An opening is formed in the dielectric layer. A portion of the etch stop layer is etched away at the opening to expose at least a portion of the silicide layer therebeneath. The etch chemistry mixture used during the etching step preferably includes hydrogen gas. The change in sheet resistance for the exposed silicide layer portion at the opening after the etching step, as compared to before the etching step, is preferably not greater than about 0.10 ohms/square.
摘要翻译：提供一种制造半导体器件的方法。在衬底上形成硅化镍层（例如NiSi）。接下来，可以在硅化物层上进行氢等离子体处理，这可能在硅化物层中引起金属/硅氢化物键的形成。在硅化物层之上形成蚀刻停止层。在蚀刻停止层上方形成介电层。在电介质层中形成开口。蚀刻停止层的一部分在开口处被蚀刻掉以暴露其下面的硅化物层的至少一部分。在蚀刻步骤期间使用的蚀刻化学混合物优选包括氢气。与蚀刻步骤之前相比，在蚀刻步骤之后的开口处的暴露的硅化物层部分的薄层电阻的变化优选不大于约0.10欧姆/平方。

6. 发明授权

US07400401B2 Measuring low dielectric constant film properties during processing 有权
标题翻译：在加工期间测量低介电常数膜性能
公开(公告)号：US07400401B2
公开(公告)日：2008-07-15
申请号：US11096049
申请日：2005-03-31
申请人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
发明人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
IPC分类号： G01J4/00
CPC分类号： G01N21/211
摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.
摘要翻译：用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质使用微波光谱仪恒定并导出介电常数的偶极分量。测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

7. 发明授权

US07378308B2 CMOS devices with improved gap-filling 有权
标题翻译：具有改进间隙填充的CMOS器件
公开(公告)号：US07378308B2
公开(公告)日：2008-05-27
申请号：US11393369
申请日：2006-03-30
申请人： Ju-Wang Hsu , Chih-Hsin Ko , Jyu-Horng Shieh , Baw-Ching Perng , Syun-Ming Jang
发明人： Ju-Wang Hsu , Chih-Hsin Ko , Jyu-Horng Shieh , Baw-Ching Perng , Syun-Ming Jang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843 , Y10S438/981
摘要： A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.
摘要翻译：半导体结构包括衬底和在衬底的第一区域上的第一MOS器件，其中第一MOS器件包括第一间隔衬垫。半导体结构还包括在第二区域上的第二MOS器件，其中第二MOS器件包括第二间隔衬垫。在第一MOS器件上形成具有第一厚度的第一应力膜，并直接在第一间隔衬垫上。在第二MOS器件上形成具有第二厚度的第二应力膜，并且直接在第二间隔衬垫上。第一和第二应力膜可以由相同的材料形成。

8. 发明申请

US20060220653A1 Measuring low dielectric constant film properties during processing 有权
标题翻译：在加工期间测量低介电常数膜性能
公开(公告)号：US20060220653A1
公开(公告)日：2006-10-05
申请号：US11096049
申请日：2005-03-31
申请人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
发明人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
IPC分类号： G01R31/00 , G01N21/00 , G01J4/00
CPC分类号： G01N21/211
摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.
摘要翻译：用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质使用微波光谱仪恒定并导出介电常数的偶极分量。测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

9. 发明授权

US08564133B2 Chip package and method for forming the same 有权
标题翻译：芯片封装及其形成方法
公开(公告)号：US08564133B2
公开(公告)日：2013-10-22
申请号：US12860823
申请日：2010-08-20
申请人： Ying-Nan Wen , Baw-Ching Perng , Wei-Ming Chen , Shu-Ming Chang
发明人： Ying-Nan Wen , Baw-Ching Perng , Wei-Ming Chen , Shu-Ming Chang
IPC分类号： H01L23/52
CPC分类号： H01L23/3135 , H01L21/76898 , H01L23/147 , H01L23/3121 , H01L23/481 , H01L23/49827 , H01L24/16 , H01L24/24 , H01L24/28 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2224/24051 , H01L2224/24226 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/8314 , H01L2224/8385 , H01L2224/92 , H01L2224/92244 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/12041 , H01L2924/12044 , H01L2924/1461 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer.
摘要翻译：根据本发明的实施例，提供了一种芯片封装。芯片封装包括具有上表面和相对的下表面的半导体衬底，穿过半导体衬底的上表面和下表面的通孔，设置在半导体衬底的上表面上的芯片，覆盖所述通孔的侧壁电连接所述芯片，覆盖所述半导体衬底的上表面的第一绝缘层，覆盖所述半导体衬底的下表面的第二绝缘层和设置在所述半导体衬底的下表面上的接合结构半导体衬底，其中所述第二绝缘层的材料与所述第一绝缘层的材料不同。

10. 发明授权

US08053894B2 Surface treatment of metal interconnect lines 有权
标题翻译：金属互连线的表面处理
公开(公告)号：US08053894B2
公开(公告)日：2011-11-08
申请号：US11213238
申请日：2005-08-26
申请人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
发明人： Wen-Kai Wan , Yih-Hsiung Lin , Ming-Ta Lei , Baw-Ching Perng , Cheng-Chung Lin , Chia-Hui Lin , Ai-Sen Liu
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76886
摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.
摘要翻译：用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层）相互作用形成合金层。合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

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