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1. 发明申请

US20130139035A1 LDPC Erasure Decoding for Flash Memories 有权
标题翻译： Flash存储器的LDPC擦除解码
公开(公告)号：US20130139035A1
公开(公告)日：2013-05-30
申请号：US13583617
申请日：2011-03-11
申请人： Hao Zhong , Yan Li , Radoslav Danilak , Earl T. Cohen
发明人： Hao Zhong , Yan Li , Radoslav Danilak , Earl T. Cohen
IPC分类号： G06F11/10
CPC分类号： H03M13/3715 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C29/52 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/373 , H03M13/6502
摘要： A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.
摘要翻译：固态盘（SSD）控制器使用LDPC解码来实现具有改进的延迟和/或纠错能力的闪速存储器访问。使用BER小于预定值的SLC闪速存储器，SSD控制器使用1位读（单读）硬判决LDPC解码器访问闪速存储器。如果硬判决LDPC解码器检测到不可校正的错误，则SSD控制器使用1.5位读（两读）擦除判决LDPC解码器来访问闪速存储器。对于具有两个其它预定值之间的原始BER的闪速存储器，SSD控制器省略硬判决LDPC解码器的使用，并且仅使用擦除判决LDPC解码器来访问闪速存储器。 SSD控制器的变化类似地访问MLC闪存。一些SSD控制器基于动态解码器选择标准动态地在硬判决和基于擦除的解码器之间切换。

2. 发明授权

US08935595B2 LDPC erasure decoding for flash memories 有权
标题翻译：闪存的LDPC擦除解码
公开(公告)号：US08935595B2
公开(公告)日：2015-01-13
申请号：US13583617
申请日：2011-03-11
申请人： Hao Zhong , Yan Li , Radoslav Danilak , Earl T Cohen
发明人： Hao Zhong , Yan Li , Radoslav Danilak , Earl T Cohen
IPC分类号： G06F11/10 , G11C11/56 , G11C16/10 , G11C16/26 , H03M13/11 , H03M13/37
CPC分类号： H03M13/3715 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C29/52 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/373 , H03M13/6502
摘要： A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.
摘要翻译：固态盘（SSD）控制器使用LDPC解码来实现具有改进的延迟和/或纠错能力的闪速存储器访问。使用BER小于预定值的SLC闪速存储器，SSD控制器使用1位读（单读）硬判决LDPC解码器访问闪速存储器。如果硬判决LDPC解码器检测到不可校正的错误，则SSD控制器使用1.5位读（两读）擦除判决LDPC解码器来访问闪速存储器。对于具有两个其它预定值之间的原始BER的闪速存储器，SSD控制器省略硬判决LDPC解码器的使用，并且仅使用擦除判决LDPC解码器来访问闪速存储器。 SSD控制器的变化类似地访问MLC闪存。一些SSD控制器基于动态解码器选择标准动态地在硬判决和基于擦除的解码器之间切换。

3. 发明申请

US20140136927A1 ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE 审中-公开
标题翻译：用于基于闪存存储器的数据存储的自适应ECC技术
公开(公告)号：US20140136927A1
公开(公告)日：2014-05-15
申请号：US13879383
申请日：2011-10-26
申请人： Yan Li , Hao Zhong , Radoslav Danilak , Earl T Cohen
发明人： Yan Li , Hao Zhong , Radoslav Danilak , Earl T Cohen
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1068 , G06F11/1016 , G06F11/1048 , G11C11/5628 , G11C29/52 , H03M13/05 , H03M13/2906
摘要： Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time.
摘要翻译：与闪存一起使用的自适应ECC技术可以改善闪存的使用寿命，可靠性，性能和/或存储容量。这些技术包括具有各种码率和/或各种码长（提供不同的纠错能力）的ECC方案和错误统计收集/跟踪（例如经由专用的硬件逻辑块）。所述技术还包括根据ECC方案中的一个或多个的编码/解码，以及至少部分地基于来自错误统计收集/跟踪的信息（例如，经由硬件逻辑自适应编解码器，从专用误差统计收集/跟踪硬件逻辑块接收输入）。这些技术还包括随着时间的推移，以各种操作模式（例如，作为MLC页面或SLC页面）选择性地操作闪存的一部分（例如，页面，块）。

4. 发明授权

US08719663B2 Cross-decoding for non-volatile storage 有权
标题翻译：用于非易失性存储的交叉解码
公开(公告)号：US08719663B2
公开(公告)日：2014-05-06
申请号：US13323769
申请日：2011-12-12
申请人： Yan Li , Hao Zhong
发明人： Yan Li , Hao Zhong
IPC分类号： G11C29/00
CPC分类号： G06F11/076 , G06F11/1072 , G06F12/0246 , G06F2212/7202 , H03M13/1102 , H03M13/2957
摘要： Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages. Alternatively the controller adjusts the allocation to maximize total usable capacity by allocating to redundancy and data for the various pages, assuming that cross-decoding is to be used.
摘要翻译：当对多级单元技术闪存的期望页进行解码时，交叉解码协助解码否则不可校正的错误。固态盘（SSD）控制器分别在各种页面（例如，上，中，下页）中调整分配给冗余的空间，使得各页具有相应的有效误码率（BER），可选地包括交叉解码，相互接近或者，控制器调整分配以均衡解码时间（或者可选地，访问时间），可选地包括当存在否则不可校正的错误时由于交叉解码而产生的解码时间（访问时间）。调整是通过（a）用于ECC冗余的分配和用户数据空间之间的相应比率，和/或（b）各种页面中的每一个的相应编码率和/或编码技术。或者，控制器通过分配冗余和各种页面的数据来调整分配以最大化总可用容量，假设要使用交叉解码。

5. 发明授权

US09329948B2 Measuring cell damage for wear leveling in a non-volatile memory 有权
标题翻译：在非易失性存储器中测量电容器损坏
公开(公告)号：US09329948B2
公开(公告)日：2016-05-03
申请号：US13620982
申请日：2012-09-15
申请人： Yan Li , Alexander Hubris , Hao Zhong
发明人： Yan Li , Alexander Hubris , Hao Zhong
IPC分类号： G11C29/00 , G06F11/16 , G06F12/02 , G11C16/34 , G11C29/42 , G11C29/50 , G11C29/52
CPC分类号： G06F11/1666 , G06F12/0246 , G06F2212/7211 , G11C16/3495 , G11C29/42 , G11C29/50 , G11C29/52
摘要： An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM.
摘要翻译： NVM控制器测量NVM中磨损均衡的单元损坏，从而提高存储子系统（如SSD）的性能，可靠性，寿命和/或成本。在第一方面，控制器确定读取NVM的页面的错误是由于单元损坏和/或单元泄漏引起的。控制器重新编程并立即读回页面，如果在立即读取期间检测到错误，则检测到错误是由单元损坏引起的。在第二方面，通过更新针对NVM的页面和/或块的单元损坏计数器跟踪单元损坏。在第三方面，至少部分地基于对NVM的页面和/或块的所测量的单元损坏来执行损耗均衡。

6. 发明授权

US08773790B2 Systems and methods for dynamic scaling in a read data processing system 有权
标题翻译：读取数据处理系统中动态缩放的系统和方法
公开(公告)号：US08773790B2
公开(公告)日：2014-07-08
申请号：US13126748
申请日：2009-04-28
申请人： Weijun Tan , Shaohua Yang , Kelly Fitzpatrick , Zongwang Li , Hao Zhong
发明人： Weijun Tan , Shaohua Yang , Kelly Fitzpatrick , Zongwang Li , Hao Zhong
IPC分类号： G11B5/09 , G11B20/10 , G11B7/00 , G06F7/00 , G06F15/00
CPC分类号： G11B20/1803 , G11B20/10222 , G11B2020/10722 , G11B2020/10759 , G11B2020/1287 , G11B2020/1289 , G11B2020/185 , H03M13/1111 , H03M13/112 , H03M13/2957 , H03M13/3746 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括提供解码输出的解码器电路的数据处理系统，以及至少部分地基于解码输出来确定第一动态缩放值和第二动态缩放值的动态标量计算电路。第一乘法器电路将解码输出乘以第一动态缩放值并提供第一缩放输出。检测器电路接收第一缩放输出并提供检测输出。第二乘法器电路将检测到的输出乘以第二动态缩放值，并提供第二缩放输出。

7. 发明授权

US08458553B2 Systems and methods for utilizing circulant parity in a data processing system 有权
标题翻译：在数据处理系统中利用循环奇偶校验的系统和方法
公开(公告)号：US08458553B2
公开(公告)日：2013-06-04
申请号：US12510885
申请日：2009-07-28
申请人： Hao Zhong , Weijun Tan , Yang Han , Zongwang Li , Shaohua Yang , Yuan Xing Lee
发明人： Hao Zhong , Weijun Tan , Yang Han , Zongwang Li , Shaohua Yang , Yuan Xing Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/1128 , H03M13/098 , H04L1/0041 , H04L1/0045 , H04L1/0057
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes receiving a codeword that has at least a first circulant with a plurality of data bits and a first circulant parity bit, a second circulant with a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits. The methods further include decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, performing a first circulant parity check on the first circulant, and performing a second circulant parity check on the second circulant.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种用于数据处理的方法，其包括：接收具有至少第一循环的码字，其具有多个数据位和第一循环奇偶校验位，第二循环具有多个数据位和第二循环奇偶校验位，以及一个或多个码字奇偶校验位。所述方法还包括使用所述一个或多个码字奇偶校验比特来解码所述码字，以访问所述第一循环和所述第二循环，对所述第一循环执行第一循环奇偶校验，以及对所述第二循环执行第二循环奇偶校验。

8. 发明授权

US08245120B2 Power reduced queue based data detection and decoding systems and methods for using such 有权
标题翻译：基于功率减少队列的数据检测和解码系统及使用方法
公开(公告)号：US08245120B2
公开(公告)日：2012-08-14
申请号：US12270713
申请日：2008-11-13
申请人： Changyou Xu , Shaohua Yang , Hao Zhong , Nils Graef , Ching-Fu Wu
发明人： Changyou Xu , Shaohua Yang , Hao Zhong , Nils Graef , Ching-Fu Wu
IPC分类号： G06F11/00
CPC分类号： H04L1/0051 , H04L1/0057 , H04L1/0071
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a variable iteration data processing system is disclosed that includes a first detector, a second detector, a decoder and a unified memory buffer. An input data set is received by the first detector that performs a data detection and provides a first detected data set. The decoder receives a derivative of the first detected data set and performs a decoding operation that yields a decoded data set. In some cases, the derivative of the first detected data set is an interleaved version of the first detected data set. The decoded data set is written to a unified memory buffer. The first decoded data set is retrievable from the unified memory buffer and a derivative thereof is provided to the second detector. In some cases, the derivative of the decoded is a de-interleaved version of the decoded data set. The second detector is operable to perform a data detection on the derivative of the decoded data set and to provide a second detected data set that is written to the unified memory buffer.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括第一检测器，第二检测器，解码器和统一存储器缓冲器的可变迭代数据处理系统。由执行数据检测的第一检测器接收输入数据集，并提供第一检测数据集。解码器接收第一检测数据集的导数，并执行产生解码数据集的解码操作。在一些情况下，第一检测数据集的导数是第一检测数据集的交错版本。解码的数据集被写入统一的存储缓冲器。第一解码数据集可从统一存储器缓冲器检索，并且其导数被提供给第二检测器。在一些情况下，解码的导数是解码数据集的解交织版本。第二检测器可操作以对解码数据集的导数执行数据检测，并提供写入统一存储器缓冲器的第二检测数据集。

9. 发明授权

US07930621B2 Systems and methods for LDPC decoding with post processing 有权
标题翻译：具有后处理的LDPC解码的系统和方法
公开(公告)号：US07930621B2
公开(公告)日：2011-04-19
申请号：US11756736
申请日：2007-06-01
申请人： Hao Zhong
发明人： Hao Zhong
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/1111 , H03M13/1102 , H03M13/3715 , H03M13/3738 , H03M13/451 , H03M13/6513
摘要： Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a method for post processing error correction in a decoder system is disclosed. The method includes receiving and iteratively decoding a soft input to generate a hard output associated with the soft input. The method further includes post processing when a plurality of parity checks fail. At least one bit of the hard output is identified as being potentially incorrect. The identified bit is modified, and the plurality of parity checks is thereafter repeated.
摘要翻译：本发明的各种实施例提供了用于解码编码信息的系统和方法。例如，公开了一种在解码器系统中进行后处理纠错的方法。该方法包括接收和迭代地解码软输入以产生与软输入相关联的硬输出。该方法还包括当多个奇偶校验检查失败时的后处理。硬输出的至少一位被识别为可能不正确。所识别的位被修改，然后重复多个奇偶校验。

10. 发明申请

US20100275096A1 Systems and Methods for Hard Decision Assisted Decoding 有权
标题翻译：硬判决辅助解码的系统和方法
公开(公告)号：US20100275096A1
公开(公告)日：2010-10-28
申请号：US12430927
申请日：2009-04-28
申请人： Hao Zhong , Shaohua Yang , Weijun Tan , Changyou Xu , Yuan Xing Lee
发明人： Hao Zhong , Shaohua Yang , Weijun Tan , Changyou Xu , Yuan Xing Lee
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H03M13/1111 , H03M13/1108 , H03M13/1128 , H03M13/3715 , H03M13/6331
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing buffer and a hard decision decoder. The queuing buffer is operable to store the soft decision output, and the hard decision decoder accesses the soft decision output and applies a hard decoding algorithm to yield a second hard decision output. The data detector is operable to perform a data detection on a derivative of the soft decision output if the soft decision decoder and the hard decision decoder fail to converge
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了一种包括具有数据检测器和软判决解码器的处理环路电路的数据处理系统。数据检测器提供检测输出，软判决解码器将软解码算法应用于检测输出的导数，以产生软决策输出和第一硬决策输出。该系统还包括排队缓冲器和硬判决解码器。排队缓冲器可操作以存储软判决输出，并且硬判决解码器访问软决策输出并应用硬解码算法以产生第二硬决策输出。如果软判决解码器和硬判决解码器不能收敛，则数据检测器可操作以对软决策输出的导数执行数据检测

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