专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5858844A Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process 失效
标题翻译：通过优化多晶氧化物工艺构建和制造亚微米场效应晶体管的方法
公开(公告)号：US5858844A
公开(公告)日：1999-01-12
申请号：US485871
申请日：1995-06-07
申请人： Hao Fang , Farrokh Omid-Zehoor , Todd Lukanc , Chris Schmidt
发明人： Hao Fang , Farrokh Omid-Zehoor , Todd Lukanc , Chris Schmidt
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28211 , H01L21/28114 , H01L29/42368 , H01L29/6659
摘要： The present invention comprises an innovative gate oxidation process after the disposition of the gate and prior to the disposition of the source and the drain by exposing the gate to oxygen at a predetermined temperature and for a predetermined time period for the optimized transistor performance. During the innovative gate oxidation process, oxygen penetrates into the interfaces of the gate conductive layer gate oxide and the gate dielectric layer silicon substrate and oxidizes portions of the gate conductive layer at the interfaces due to the oxygen smiling or the bird beak effect, which results in an increased effective thickness of the gate dielectric layer. Optionally, HCl can be introduced at a predetermined flowrate during the innovative gate oxidation process. A particular embodiment of the present invention is the fabrication of MOS transistors with polysilicon as the gate conductive layer and silicon oxide as the gate dielectric layer, and with the source and drain fabricated by the low doped drain (LDD) implant. In this particular case, the innovative gate oxidation process is a polysilicon oxidation (POX) process grown before LDD implant. The oxidation temperature and oxidation time duration for optimized transistor performances have been found to be 850.degree. C. and 115 minutes, respectively. This present invention is utilized to achieve maximum speed and performance by optimizing the POX process.
摘要翻译：本发明包括在门的配置之后并且在通过在预定温度下将栅极暴露于氧气并在预定时间段内对于优化的晶体管性能进行设置之前的创新的栅极氧化工艺。在创新的栅极氧化过程中，氧气渗透入栅极导电层栅极氧化物和栅极电介质层硅衬底的界面，并由于氧气微笑或鸟喙效应而在界面处氧化栅极导电层的部分，从而导致在栅介电层的有效厚度增加。任选地，可以在创新的栅极氧化过程期间以预定流量引入HCl。本发明的一个具体实施例是制造具有多晶硅作为栅极导电层和氧化硅作为栅极介电层的MOS晶体管，并且通过低掺杂漏极（LDD）注入制造源极和漏极。在这种特殊情况下，创新的栅极氧化工艺是在LDD植入之前生长的多晶硅氧化（POX）工艺。已经发现优化的晶体管性能的氧化温度和氧化时间分别为850℃和115分钟。本发明用于通过优化POX过程来实现最大速度和性能。

2. 发明授权

US08003545B2 Method of forming an electronic device including forming features within a mask and a selective removal process 有权
标题翻译：形成电子设备的方法，包括在掩模内形成特征和选择性去除过程
公开(公告)号：US08003545B2
公开(公告)日：2011-08-23
申请号：US12031458
申请日：2008-02-14
申请人： Todd Lukanc , Hung-Eil Kim
发明人： Todd Lukanc , Hung-Eil Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/32137
摘要： A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature.
摘要翻译：形成电子器件的方法可以包括形成覆盖下层的图案化掩模层，使得掩模层具有第一特征，第二特征和第三特征，并且第一特征位于第二特征和第三特征之间。第一特征可以通过掩模层中的第一开口与第二特征间隔开，并且可以通过掩模层中的第二开口与第三特征间隔开。该方法还可以包括选择性地移除第一开口，第二开口，第二特征和第三特征之下的下层的部分，并且还移除第二特征和第三特征，同时留下基本上所有的第一特征和第一个特征下的下层的重要部分。

3. 发明申请

US20070209030A1 SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES 有权
标题翻译：使用光学规则检查分辨率增强技术的集成电路设备和制造的系统和方法
公开(公告)号：US20070209030A1
公开(公告)日：2007-09-06
申请号：US11741845
申请日：2007-04-30
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

4. 发明授权

US06635409B1 Method of strengthening photoresist to prevent pattern collapse 有权
标题翻译：加强光致抗蚀剂以防止图案塌陷的方法
公开(公告)号：US06635409B1
公开(公告)日：2003-10-21
申请号：US09902568
申请日：2001-07-12
申请人： Christopher F. Lyons , Scott A. Bell , Todd Lukanc , Marina V. Plat
发明人： Christopher F. Lyons , Scott A. Bell , Todd Lukanc , Marina V. Plat
IPC分类号： G03F700
CPC分类号： G03F7/40 , G03F7/2024
摘要： There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a treated photoresist and a composition for a treatable photoresist.
摘要翻译：提供了一种形成光刻应用的光致抗蚀剂层的方法，其具有增加的结构强度。光致抗蚀剂层通过掩模曝光并显影。然后在光致抗蚀剂层干燥之前，处理光致抗蚀剂层以改变其材料性质。还提供了使用经处理的光致抗蚀剂和用于可处理光致抗蚀剂的组合物的半导体制造方法。

5. 发明授权

US06633083B2 Barrier layer integrity test 失效
标题翻译：阻隔层完整性测试
公开(公告)号：US06633083B2
公开(公告)日：2003-10-14
申请号：US09514413
申请日：2000-02-28
申请人： Christy Mei-Chu Woo , Young-Chang Joo , Todd Lukanc
发明人： Christy Mei-Chu Woo , Young-Chang Joo , Todd Lukanc
IPC分类号： H01L3106
CPC分类号： H01L22/34
摘要： A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing CV or IV measurements between the copper lines and the silicon wafer.
摘要翻译：一种用于确定集成电路制造中多级铜金属化结构的阻挡层完整性的结构和方法。新的测试结构防止铜CMP的任何导电残余物扩散到电介质层中。通过在铜线和硅晶片之间执行CV或IV测量来测试阻挡层的完整性

6. 发明授权

US06184114B2 MOS transistor formation 有权
标题翻译： MOS晶体管的形成
公开(公告)号：US06184114B2
公开(公告)日：2001-02-06
申请号：US09375503
申请日：1999-08-17
申请人： Todd Lukanc
发明人： Todd Lukanc
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/823842 , H01L29/517
摘要： Semiconductor devices of different conductivity types with optimized gate electrodes are formed on a semiconductor substrate by replacing the initial gate electrode and, optionally, the underlying gate oxide layer. Embodiments include forming a first gate electrode on a gate oxide layer and replacing the gate electrode with a second gate electrode. Optionally, a second dielectric layer can be deposited in place of or in addition to the gate oxide layer prior to depositing the second gate electrode.
摘要翻译：通过替换初始栅极电极和任选地下面的栅极氧化物层，在半导体衬底上形成具有优化的栅电极的不同导电类型的半导体器件。实施例包括在栅氧化层上形成第一栅电极，用第二栅电极代替栅电极。可选地，在沉积第二栅极电极之前，第二电介质层可以代替栅氧化物层或除栅极氧化物层之外沉积。

7. 发明申请

US20090209107A1 METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING FEATURES WITHIN A MASK AND A SELECTIVE REMOVAL PROCESS 有权
标题翻译：形成电子装置的方法，包括在掩模中形成特征和选择性去除过程
公开(公告)号：US20090209107A1
公开(公告)日：2009-08-20
申请号：US12031458
申请日：2008-02-14
申请人： Todd Lukanc , Hung-Eil Kim
发明人： Todd Lukanc , Hung-Eil Kim
IPC分类号： H01L21/306
CPC分类号： H01L21/32139 , H01L21/32137
摘要： A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature.
摘要翻译：形成电子器件的方法可以包括形成覆盖下层的图案化掩模层，使得掩模层具有第一特征，第二特征和第三特征，并且第一特征位于第二特征和第三特征之间。第一特征可以通过掩模层中的第一开口与第二特征间隔开，并且可以通过掩模层中的第二开口与第三特征间隔开。该方法还可以包括选择性地移除第一开口，第二开口，第二特征和第三特征之下的下层的部分，并且还移除第二特征和第三特征，同时留下基本上所有的第一特征和第一个特征下的下层的重要部分。

8. 发明授权

US07487492B1 Method for increasing manufacturability of a circuit layout 有权
标题翻译：提高电路布局可制造性的方法
公开(公告)号：US07487492B1
公开(公告)日：2009-02-03
申请号：US11437312
申请日：2006-05-19
申请人： Ajay Singhal , Todd Lukanc
发明人： Ajay Singhal , Todd Lukanc
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： According to one exemplary embodiment, a method for increasing manufacturability of a circuit layer includes determining a threshold value for at least one image property from a repetitive section of the circuit layout. According to this embodiment, the method further includes performing a simulated lithographic process using the circuit layout to determine a number of simulated values of the at least one image property for a non-repetitive section of the circuit layout. The method further includes comparing each of the simulated values with the threshold value to determine printability of the non-repetitive section of the circuit layout prior to lithographically printing the circuit layout on a wafer. The method further includes modifying the non-repetitive section of the circuit layout if the threshold value is greater than at least one of the simulated values. By modifying the non-repetitive section of the circuit layout, manufacturability of the circuit layout can be increased.
摘要翻译：根据一个示例性实施例，用于提高电路层的可制造性的方法包括从电路布局的重复部分确定至少一个图像特性的阈值。根据本实施例，该方法还包括使用电路布局来执行模拟光刻处理，以确定电路布局的非重复部分的至少一个图像特性的模拟值的数量。该方法还包括将每个模拟值与阈值进行比较，以在光刻印刷晶片上的电路布局之前确定电路布局的非重复部分的可印刷性。该方法还包括如果阈值大于至少一个模拟值，则修改电路布局的非重复部分。通过修改电路布局的非重复部分，可以提高电路布局的可制造性。

9. 发明申请

US20050229125A1 System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques 有权
标题翻译：使用光学规则检查进行集成电路器件设计和制造的屏幕分辨率增强技术的系统和方法
公开(公告)号：US20050229125A1
公开(公告)日：2005-10-13
申请号：US10816764
申请日：2004-04-02
申请人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
发明人： Cyrus Tabery , Todd Lukanc , Chris Haidinyak , Luigi Capodieci , Carl Babcock , Hung-eil Kim , Christopher Spence
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G03F7/70433 , G03F7/705
摘要： A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).
摘要翻译：选择用于在晶片上构图布局的多个光刻工艺参数的方法包括模拟布局如何在晶片上印刷多个分辨率增强技术（RET），其中每个RET对应于多个光刻工艺参数。对于每个RET，模拟布局中的结构边缘可以基于可制造性进行分类。可以选择提供最佳可制造性的RET。以这种方式，仿真工具可用于确定扫描仪设置和掩模版类型的最佳组合，以最小化晶片临界尺寸（CD）的变化。

10. 发明授权

US06279147B1 Use of an existing product map as a background for making test masks 失效
标题翻译：使用现有的产品图作为测试口罩的背景
公开(公告)号：US06279147B1
公开(公告)日：2001-08-21
申请号：US09540365
申请日：2000-03-31
申请人： Matthew S. Buynoski , Ramkumar Subramanian , Todd Lukanc
发明人： Matthew S. Buynoski , Ramkumar Subramanian , Todd Lukanc
IPC分类号： G03F900
CPC分类号： H01L22/34 , G03F1/44
摘要： One aspect of the present invention relates to a method of making a test mask, involving the steps of providing an existing product mask pattern having a first pattern thereon; removing a portion of the first pattern from the existing product mask pattern; and forming a test pattern in the portion of the existing product mask pattern to provide the test mask, wherein the first pattern of the existing product mask pattern is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern. Another aspect of the present invention relates to a test mask, containing a wall paper portion comprising a first pattern from an existing product mask pattern; and a test portion comprising a test pattern, wherein the first pattern of the existing product mask pattern is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern.
摘要翻译：本发明的一个方面涉及一种制造测试掩模的方法，包括以下步骤：提供其上具有第一图案的现有产品掩模图案; 从现有产品掩模图案中去除第一图案的一部分; 并且在现有产品掩模图案的部分中形成测试图案以提供测试掩模，其中现有产品掩模图案的第一图案在图案密度，图案变化性，图案尺寸，图案形状中的至少一个中基本相似，优先方向和模式划线与测试模式。本发明的另一方面涉及一种测试掩模，其包含墙纸部分，其包含来自现有产品掩模图案的第一图案; 以及包括测试图案的测试部分，其中现有产品掩模图案的第一图案在图案密度，图案变化性，图案尺寸，图案形状，优先方向和具有测试图案的图案划线中的至少一个中基本相似。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式