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1. 发明授权

US6054342A Method of making integrated circuits with tub-ties 有权
标题翻译：制造集成电路的方法
公开(公告)号：US6054342A
公开(公告)日：2000-04-25
申请号：US339306
申请日：1999-06-23
申请人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
发明人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
IPC分类号： H01L21/266 , H01L21/761 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/76202 , H01L21/266 , H01L21/761 , H01L21/76218 , H01L21/823892
摘要： An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.In accordance with another aspect of our invention, a reduced-mask-count CMOS IC process includes forming the isolating regions so that each has a protrusion which extends over the surface regions where the peripheral sections of the cap portion are to be formed. Then, a combination of ion implantation energies and concentrations, as well as suitable PR masking, in conjunction with the shape of the isolating regions, enables selective doping of the pedestal portion.
摘要翻译： IC包括第一导电类型的桶，嵌入在桶中的至少一个晶体管，以及第一对隔离区域，其中限定了耦合到桶的桶连接区域。连接区域包括第一导电类型的盖部分和第二导电类型的下面的埋入基座部分。基座部分的至少顶部被盖部分围绕，使得在盖部分和桶之间形成导电路径。在这种设计的CMOS IC管中，为NMOS和PMOS晶体管提供。在一个优选实施例中，每个桶带的盖部分包括相对重掺杂的中心部分和更多轻掺杂的外围部分，两者都是相同的导电类型。根据本发明的另一方面，减少掩模计数的CMOS IC工艺包括形成隔离区域，使得每个隔离区域都具有在要形成盖部分的周边部分的表面区域上延伸的突起。然后，结合隔离区域的形状，离子注入能量和浓度的组合以及合适的PR掩模能够选择性地掺杂基座部分。

2. 发明授权

US5949112A Integrated circuits with tub-ties 失效
标题翻译：集成电路与管道
公开(公告)号：US5949112A
公开(公告)日：1999-09-07
申请号：US85913
申请日：1998-05-28
申请人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
发明人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
IPC分类号： H01L21/266 , H01L21/761 , H01L21/762 , H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/76202 , H01L21/266 , H01L21/761 , H01L21/76218 , H01L21/823892
摘要： An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type. In accordance with another aspect of our invention, a reduced-mask-count CMOS IC process includes forming the isolating regions so that each has a protrusion which extends over the surface regions where the peripheral sections of the cap portion are to be formed. Then, a combination of ion implantation energies and concentrations, as well as suitable PR masking, in conjunction with the shape of the isolating regions, enables selective doping of the pedestal portion.
摘要翻译： IC包括第一导电类型的桶，嵌入在桶中的至少一个晶体管，以及第一对隔离区域，其中限定了耦合到桶的桶连接区域。连接区域包括第一导电类型的盖部分和第二导电类型的下面的埋入基座部分。基座部分的至少顶部被盖部分围绕，使得在盖部分和桶之间形成导电路径。在这种设计的CMOS IC管中，为NMOS和PMOS晶体管提供。在一个优选实施例中，每个桶带的盖部分包括相对重掺杂的中心部分和更多轻掺杂的外围部分，两者都是相同的导电类型。根据本发明的另一方面，减少掩模计数的CMOS IC工艺包括形成隔离区域，使得每个隔离区域都具有在要形成盖部分的周边部分的表面区域上延伸的突起。然后，结合隔离区域的形状，离子注入能量和浓度的组合以及合适的PR掩模能够选择性地掺杂基座部分。

3. 发明授权

US06358824B1 Integrated circuits with tub-ties and shallow trench isolation 有权
标题翻译：集成电路具有管状和浅沟槽隔离
公开(公告)号：US06358824B1
公开(公告)日：2002-03-19
申请号：US09706319
申请日：2000-11-03
申请人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
发明人： Hans-Joachim Ludwig Gossmann , Thi-Hong-Ha Vuong
IPC分类号： H01L21425
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method of fabricating an IC comprises the steps of: (a) forming trench isolation regions in a surface of a semiconductor body; and (b) forming a tub-tie region between at least one pair of the trench isolation regions (when viewed in cross-section) by a process that includes the following steps: (b1) forming a first photolithographic mask that covers and is in registration with the tub-tie region; (b2) implanting ions of a first conductivity-type to form a tub region adjacent the tub-tie region; (b3) removing the first mask; (b4) forming a second photolithographic mask that has an opening that exposes most of the underlying tub-tie region but overlaps a first peripheral section on one side of the tub-tie region; (b5) implanting ions to form a pedestal portion of a second conductivity-type within the tub-tie region; and (b6) implanting ions of the first conductivity-type at an acute (preferably non-zero) angle −⊕ with respect to the normal to the surface to the body so as to form a conductivity-type localized first zone that extends into the first peripheral section. In a preferred embodiment, the first conductivity-type tub of step (b2) and the second conductivity-type pedestal of step (b5) are formed by implanting ions at an acute (non-zero) angle +&bgr; to the normal to the surface of the body. In another embodiment, between steps (b1) and (b3), the cap portion is angle-implanted to form a highly doped peripheral localized second zone of the second conductivity type located adjacent a different portion of one of said isolating regions. The second zone prevents any significant amount of charge build-up from taking place in the pedestal portion.
摘要翻译：一种制造IC的方法包括以下步骤：（a）在半导体本体的表面中形成沟槽隔离区; 和（b）在至少一对沟槽隔离区域之间（当横截面观察时）通过包括以下步骤的工艺形成管连接区域：（b1）形成覆盖并处于其中的第一光刻掩模与领带区域注册; （b2）注入第一导电类型的离子以形成与所述连接区相邻的盆区; （b3）去除第一掩模; （b4）形成第二光刻掩模，所述第二光刻掩模具有暴露所述下面的连接区域中的大部分但与所述连接区域的一侧上的第一外围部分重叠的开口; （b5）植入离子以在所述连接区域内形成第二导电类型的基座部分; 和（b6）将第一导电类型的离子相对于表面的法线相对于身体的锐角（优选非零）角度）注入，以便形成导电类型的局部第一区，其延伸到第一个周边部分。在优选实施例中，步骤（b2）的第一导电型桶和步骤（b5）的第二导电型基座通过以与表面法线成锐角（非零）角度+β的离子注入而形成的身体。在另一个实施例中，在步骤（b1）和（b3）之间，帽部分是角度注入的，以形成位于邻近所述隔离区域之一的不同部分的第二导电类型的高度掺杂的外围局部第二区域。第二区域防止在基座部分中发生任何显着量的电荷积聚。

4. 发明授权

US06403454B1 Silicon semiconductor devices with &dgr;-doped layers 有权
标题翻译：具有δ掺杂层的硅半导体器件
公开(公告)号：US06403454B1
公开(公告)日：2002-06-11
申请号：US09430316
申请日：1999-10-29
申请人： Paul H. Citrin , Hans-Joachim Ludwig Gossmann , David Anthony Muller
发明人： Paul H. Citrin , Hans-Joachim Ludwig Gossmann , David Anthony Muller
IPC分类号： H01L2104
CPC分类号： H01L29/78 , H01L21/02381 , H01L21/02576 , H01L21/02584 , H01L29/365
摘要： We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×1020 cm−3 can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2×1021 cm−3 are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is formed as an integral part of an FET. In accordance with another aspect of our invention, an integrated circuit is fabricated by the steps of providing a single crystal silicon body and forming a doped layer in the body, characterized in that the processing steps form neither a significant amount of electrically inactive precipitates nor a significant number of deactivating dopant centers containing vacancies, and the layer is fabricated as a &dgr;-doped layer that is doped with a Group V element, so that the free-carrier density in the layer is in excess of about 7×1020 cm−3, preferably in excess of about 2×1021 cm−3.
摘要翻译：我们已经发现，与形成DP缺陷的常规智慧相反，不会发生高掺杂的2D层中的电饱和。根据本发明的一个方面，可以在掺杂有V族元素的单晶Si层中获得超过约7×10 20 cm -3的自由载流子浓度。在一个实施方案中，在掺杂Sb的单晶Si中实现超过约2×10 21 cm -3的自由载流子浓度。在另一个实施例中，Δ-掺杂层形成为FET的组成部分。根据本发明的另一方面，通过以下步骤制造集成电路：提供单晶硅体并在体内形成掺杂层，其特征在于，所述加工步骤既不形成大量的电不活泼的沉淀物也不形成显着数量的包含空位的失活掺杂剂中心，并且该层被制造为掺杂有V族元素的δ掺杂层，使得该层中的自由载流子密度超过约7×10 20 cm -3，优选超过约2×1021cm-3。

5. 发明授权

US5731626A Process for controlling dopant diffusion in a semiconductor layer and semiconductor layer formed thereby 失效
标题翻译：用于控制由其形成的半导体层和半导体层中的掺杂剂扩散的方法
公开(公告)号：US5731626A
公开(公告)日：1998-03-24
申请号：US862226
申请日：1997-05-23
申请人： David James Eaglesham , Hans-Joachim Ludwig Gossmann , John Milo Poate , Peter Adriaan Stolk
发明人： David James Eaglesham , Hans-Joachim Ludwig Gossmann , John Milo Poate , Peter Adriaan Stolk
IPC分类号： H01L21/20 , H01L21/203 , H01L21/205 , H01L21/22 , H01L21/265 , H01L29/08 , H01L29/10 , H01L29/167 , H01L29/786
CPC分类号： H01L29/78684 , H01L21/22 , H01L21/26546 , H01L29/0847 , H01L29/1079 , H01L29/167 , H01L21/02381 , H01L21/02532 , H01L21/0262 , Y10S438/916 , Y10S438/918
摘要： Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.
摘要翻译：通过至少一种晶体生长技术在半导体层中引入电惰性杂质来控制离子注入掺杂剂的扩散。

6. 发明授权

US6153920A Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby 失效
标题翻译：用于控制半导体层中的掺杂剂扩散的方法和由此形成的半导体器件
公开(公告)号：US6153920A
公开(公告)日：2000-11-28
申请号：US15981
申请日：1998-01-30
申请人： Hans-Joachim Ludwig Gossmann , Conor Stefan Rafferty
发明人： Hans-Joachim Ludwig Gossmann , Conor Stefan Rafferty
IPC分类号： H01L21/205 , H01L21/22 , H01L21/265 , H01L29/08 , H01L29/10 , H01L29/167 , H01L29/786
CPC分类号： H01L29/78684 , H01L21/22 , H01L21/26546 , H01L29/0847 , H01L29/1079 , H01L29/167
摘要： A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such that the carbon atoms absorb point defects created in the substrate during device fabrication but do not adversely affect the leakage characteristics of the device.
摘要翻译：公开了具有有利浓度分布的含碳区域的半导体器件。将碳引入到衬底的区域中并且在器件的空间电荷层下方的深度处，并且浓度使得碳原子吸收在器件制造期间在衬底中产生的点缺陷，但不会不利地影响漏电特性的设备。

7. 发明授权

US6043139A Process for controlling dopant diffusion in a semiconductor layer 失效
标题翻译：用于控制半导体层中的掺杂剂扩散的方法
公开(公告)号：US6043139A
公开(公告)日：2000-03-28
申请号：US563688
申请日：1995-11-28
申请人： David James Eaglesham , Hans-Joachim Ludwig Gossmann , John Milo Poate , Peter Adriaan Stolk
发明人： David James Eaglesham , Hans-Joachim Ludwig Gossmann , John Milo Poate , Peter Adriaan Stolk
IPC分类号： H01L21/20 , H01L21/203 , H01L21/205 , H01L21/22 , H01L21/265 , H01L29/08 , H01L29/10 , H01L29/167 , H01L29/786
CPC分类号： H01L29/78684 , H01L21/22 , H01L21/26546 , H01L29/0847 , H01L29/1079 , H01L29/167 , H01L21/02381 , H01L21/02532 , H01L21/0262 , Y10S438/916 , Y10S438/918
摘要： Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.
摘要翻译：通过至少一种晶体生长技术在半导体层中引入电惰性杂质来控制离子注入掺杂剂的扩散。

8. 发明授权

US06632728B2 Increasing the electrical activation of ion-implanted dopants 有权
标题翻译：增加离子注入掺杂剂的电活化
公开(公告)号：US06632728B2
公开(公告)日：2003-10-14
申请号：US09906211
申请日：2001-07-16
申请人： Hans-Joachim Ludwig Gossmann , Conor Stefan Rafferty , Tony E. Haynes , Ramki Kalyanaraman , Vincent C. Venezia , Maria Lourdes Pelaz-Montes
发明人： Hans-Joachim Ludwig Gossmann , Conor Stefan Rafferty , Tony E. Haynes , Ramki Kalyanaraman , Vincent C. Venezia , Maria Lourdes Pelaz-Montes
IPC分类号： H01L21265
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/66575
摘要： We have found that under certain prescribed conditions a co-implantation process can be effective in increasing the electrical activation of implanted dopant ions. In accordance with one aspect of our invention, a method of making a semiconductor device includes the steps of providing a single crystal semiconductor body, implanting vacancy-generating, ions into a preselected region of the body, implanting dopant ions into the preselected region, the dopant implant forming interstitial defects in the body, and annealing the body to electrically activate the dopant ions. Importantly, in our method the vacancy-generating implant introduces vacancy defects into the preselected region that are effective to annihilate the interstitial defects. In addition, process steps that amorphize the surface of the implanted region are avoided, and the dose of the vacancy-generating implant is made to be greater than that of the dopant implant. In a preferred embodiment, the peak of the vacancy defect concentration profile substantially overlaps the peak of the dopant implant concentration profile. In another preferred embodiment the peak of the vacancy-generating implant profile is deeper than that of the dopant profile. In accordance with another aspect of our invention, after ion implantation is complete, only low temperature process steps (e.g., steps performed at temperatures no greater than about 800° C. for Si devices) are performed.
摘要翻译：我们已经发现，在某些规定条件下，共同注入工艺可以有效地增加注入的掺杂剂离子的电活化。根据本发明的一个方面，制造半导体器件的方法包括以下步骤：提供单晶半导体器件，将产生空位的离子注入到身体的预选区域中，将掺杂剂离子注入预选区域，掺杂剂注入物在体内形成间隙缺陷，并退火身体以电激活掺杂剂离子。重要的是，在我们的方法中，产生空位的植入物将缺陷缺陷引入到预选区域中，这有效地消除间质缺陷。此外，避免了植入区域的表面非晶化的工艺步骤，并且使空位产生植入物的剂量大于掺杂剂注入的剂量。在优选的实施方案中，空位缺陷浓度分布的峰值基本上与掺杂剂注入浓度分布的峰值重叠。在另一优选实施例中，产生空位的注入轮廓的峰值比掺杂剂分布的峰值更深。根据本发明的另一方面，在离子注入完成之后，仅执行低温工艺步骤（例如，对于Si器件在不高于约800℃的温度下执行的步骤）。

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