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1. 发明授权

US06403454B1 Silicon semiconductor devices with &dgr;-doped layers 有权
标题翻译：具有δ掺杂层的硅半导体器件
公开(公告)号：US06403454B1
公开(公告)日：2002-06-11
申请号：US09430316
申请日：1999-10-29
申请人： Paul H. Citrin , Hans-Joachim Ludwig Gossmann , David Anthony Muller
发明人： Paul H. Citrin , Hans-Joachim Ludwig Gossmann , David Anthony Muller
IPC分类号： H01L2104
CPC分类号： H01L29/78 , H01L21/02381 , H01L21/02576 , H01L21/02584 , H01L29/365
摘要： We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×1020 cm−3 can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2×1021 cm−3 are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is formed as an integral part of an FET. In accordance with another aspect of our invention, an integrated circuit is fabricated by the steps of providing a single crystal silicon body and forming a doped layer in the body, characterized in that the processing steps form neither a significant amount of electrically inactive precipitates nor a significant number of deactivating dopant centers containing vacancies, and the layer is fabricated as a &dgr;-doped layer that is doped with a Group V element, so that the free-carrier density in the layer is in excess of about 7×1020 cm−3, preferably in excess of about 2×1021 cm−3.
摘要翻译：我们已经发现，与形成DP缺陷的常规智慧相反，不会发生高掺杂的2D层中的电饱和。根据本发明的一个方面，可以在掺杂有V族元素的单晶Si层中获得超过约7×10 20 cm -3的自由载流子浓度。在一个实施方案中，在掺杂Sb的单晶Si中实现超过约2×10 21 cm -3的自由载流子浓度。在另一个实施例中，Δ-掺杂层形成为FET的组成部分。根据本发明的另一方面，通过以下步骤制造集成电路：提供单晶硅体并在体内形成掺杂层，其特征在于，所述加工步骤既不形成大量的电不活泼的沉淀物也不形成显着数量的包含空位的失活掺杂剂中心，并且该层被制造为掺杂有V族元素的δ掺杂层，使得该层中的自由载流子密度超过约7×10 20 cm -3，优选超过约2×1021cm-3。

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