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1. 发明授权

US06730982B2 FBEOL process for Cu metallizations free from Al-wirebond pads 失效
标题翻译：不含Al-wirebond焊盘的Cu金属化的FBEOL工艺
公开(公告)号：US06730982B2
公开(公告)日：2004-05-04
申请号：US09820900
申请日：2001-03-30
申请人： Hans-Joachim Barth , Petra Felsner , Erdem Kaltalioglu , Gerald Friese
发明人： Hans-Joachim Barth , Petra Felsner , Erdem Kaltalioglu , Gerald Friese
IPC分类号： H01L2900
CPC分类号： H01L21/76849 , H01L23/5258 , H01L24/05 , H01L24/45 , H01L2224/04042 , H01L2224/05647 , H01L2224/45124 , H01L2224/45147 , H01L2224/48747 , H01L2224/48847 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01044 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19042 , H01L2924/00014 , H01L2924/00
摘要： A process of making an interconnection structure of Cu FBEOL semiconductor devices that does not rely upon Al-wirebond pads which require additional patterning steps (for Al-via to Cu, Al-pad), including: a) providing a substrate having Cu wires and Cu pads embedded therein; b) selectively depositing a first metallic passivation layer on the top copper surfaces sufficient to prevent Cu oxidation and/or Cu out diffusion; c) depositing a final passivation layer; d) employing lithography and etching of the final passivation layer to cause pad opening of the fuses by exposing the passivated Cu in the bond pad area and in the fuse area; and e) causing additional passivation of open pad and open fuse areas by selective immersion deposition of Au.
摘要翻译：制造不依赖需要附加图形化步骤（Al-via至Cu，Al-pad）的Al-引线键合焊盘的Cu FBEOL半导体器件的互连结构的工艺，包括：a）提供具有Cu线的衬底和嵌入其中的铜焊盘; b）在顶部铜表面上选择性地沉积足以防止Cu氧化和/或Cu扩散的第一金属钝化层; c）沉积最后的钝化层; d）使用光刻和蚀刻最终钝化层通过在接合焊盘区域和保险丝区域中暴露钝化的Cu来引起熔断器的焊盘打开; 通过Au的选择性沉积沉积导致额外的开放焊盘钝化和开放的保险丝区域。

2. 发明申请

US20050282346A1 MIM capacitors 有权
标题翻译： MIM电容器
公开(公告)号：US20050282346A1
公开(公告)日：2005-12-22
申请号：US11210094
申请日：2005-08-23
申请人： Hans-Joachim Barth , Petra Felsner , Erdem Kaltalioglu , Gerald Friese
发明人： Hans-Joachim Barth , Petra Felsner , Erdem Kaltalioglu , Gerald Friese
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/318 , H01L27/08 , H01L21/336 , H01L21/20
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
摘要翻译：一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。在MIM电容器顶板上选择性地形成第二盖层。

3. 发明授权

US06451664B1 Method of making a MIM capacitor with self-passivating plates 有权
标题翻译：制造具有自钝化板的MIM电容器的方法
公开(公告)号：US06451664B1
公开(公告)日：2002-09-17
申请号：US09774251
申请日：2001-01-30
申请人： Hans-Joachim Barth , Gerald Friese , Petra Felsner
发明人： Hans-Joachim Barth , Gerald Friese , Petra Felsner
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L28/60
摘要： A method of making a metal-insulator-metal (MIM) capacitor (158) having self-passivating plates (143, 155). A liner (116) is deposited on a workpiece (112) and dielectric (114). A conductive layer (142) is deposited and annealed to form dopant-rich region (144). Insulating region (145) is formed on exposed portions of dopant-rich region (144) by exposure to atmosphere or oxygen. Capacitor dielectric layer (146) is disposed over the first capacitive plate (143). A second capacitive plate (155) is formed over the first capacitive plate (143) and capacitor dielectric layer (146). The second capacitive plate (155) is annealed to form dopant-rich region (154) and exposed to atmosphere or oxygen to form insulating region (156). Optional seed layer (140) may be deposited prior to the formation of the first capacitive plate (143).
摘要翻译：一种制造具有自钝化板（143,155）的金属 - 绝缘体 - 金属（MIM）电容器（158）的方法。衬垫（116）沉积在工件（112）和电介质（114）上。沉积并退火导电层（142）以形成富掺杂区域（144）。绝缘区域（145）通过暴露于大气或氧气而形成在富掺杂区域（144）的暴露部分上。电容电介质层（146）设置在第一电容板（143）的上方。在第一电容板（143）和电容器电介质层（146）之上形成第二电容板（155）。退火第二电容板155以形成富掺杂区域154并暴露于大气或氧气以形成绝缘区域156。可以在形成第一电容板（143）之前沉积可选种子层（140）。

4. 发明申请

US20050093159A1 Stress-relief layer for semiconductor applications 有权
标题翻译：用于半导体应用的应力消除层
公开(公告)号：US20050093159A1
公开(公告)日：2005-05-05
申请号：US10698057
申请日：2003-10-30
申请人： Hans-Joachim Barth , Erdem Kaltalioglu , Mark Hoinkis , Gerald Friese , Pak Leung
发明人： Hans-Joachim Barth , Erdem Kaltalioglu , Mark Hoinkis , Gerald Friese , Pak Leung
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.
摘要翻译：在半导体集成电路器件中，可以通过在通孔和覆盖在通孔之间的硬电介质层之间引入应力消除层来减小通孔上的热机械应力。

5. 发明授权

US07368804B2 Method and apparatus of stress relief in semiconductor structures 有权
标题翻译：半导体结构中应力消除的方法和装置
公开(公告)号：US07368804B2
公开(公告)日：2008-05-06
申请号：US10439874
申请日：2003-05-16
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
IPC分类号： H01L23/58 , H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译：提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔，通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

6. 发明申请

US20050221610A1 Method and apparatus of stress relief in semiconductor structures 审中-公开
标题翻译：半导体结构中应力消除的方法和装置
公开(公告)号：US20050221610A1
公开(公告)日：2005-10-06
申请号：US11144980
申请日：2005-06-03
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis Warner , Erdem Kaltalioglu
IPC分类号： H01L23/522 , H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译：提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔，通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

7. 发明授权

US07786007B2 Method and apparatus of stress relief in semiconductor structures 有权
标题翻译：半导体结构中应力消除的方法和装置
公开(公告)号：US07786007B2
公开(公告)日：2010-08-31
申请号：US12098976
申请日：2008-04-07
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译：提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔，通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

8. 发明申请

US20080213993A1 Method and Apparatus of Stress Relief in Semiconductor Structures 有权
标题翻译：半导体结构应力消除的方法与装置
公开(公告)号：US20080213993A1
公开(公告)日：2008-09-04
申请号：US12098976
申请日：2008-04-07
申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
发明人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
摘要翻译：提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔，通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

9. 发明授权

US06866943B2 Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level 失效
标题翻译：焊料结构包括在金属化水平顶上的钨或钨化合物层
公开(公告)号：US06866943B2
公开(公告)日：2005-03-15
申请号：US10134617
申请日：2002-04-30
申请人： Gerald Friese , Werner K. Robl , Hans-Joachim Barth , Axel Brintzinger
发明人： Gerald Friese , Werner K. Robl , Hans-Joachim Barth , Axel Brintzinger
IPC分类号： H01L23/485 , B21D39/00
CPC分类号： H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01043 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01074 , H01L2924/04941 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , Y10T428/12535 , Y10T428/12674 , Y10T428/12743 , Y10T428/12826 , Y10T428/1284 , H01L2924/00
摘要： A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma containing Cl2, the bond structure comprises: a liner or lower metal layer formed on a predetermined area of the IC substrate; an aluminum-based metal layer formed on the liner layer as the last metal layer for bond purposes; a tungsten based redundancy layer formed on top of the aluminum-based last metal layer; and a passivation layer formed over the IC substrate and on the tungsten based redundancy layer.
摘要翻译：一种形成在IC衬底的预定区域上的接合衬垫结构，包括在包含Cl 2的等离子体中的光刻和等离子体蚀刻时快速且容易地移除的冗余和钝化层，所述键结构包括：形成在预定区域上的衬垫或下金属层 IC基板; 形成在衬垫层上的铝基金属层作为用于结合目的的最后一个金属层; 形成在铝基最后金属层顶部的钨基冗余层; 以及形成在IC基板上和钨基冗余层上的钝化层。

10. 发明授权

US06720212B2 Method of eliminating back-end rerouting in ball grid array packaging 有权
标题翻译：消除球栅阵列封装中后端重路由的方法
公开(公告)号：US06720212B2
公开(公告)日：2004-04-13
申请号：US10098840
申请日：2002-03-14
申请人： Werner Robl , Thomas Goebel , Axel Christoph Brintzinger , Gerald Friese
发明人： Werner Robl , Thomas Goebel , Axel Christoph Brintzinger , Gerald Friese
IPC分类号： H01L2182
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2924/19043 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.
摘要翻译：公开了一种球栅阵列封装的方法，包括以下步骤：提供其上具有金属导体的半导体管芯，用绝缘层覆盖所述金属导体，蚀刻穿过所述绝缘层，以便向所述金属导体提供一个或多个开口沉积柔性材料层，蚀刻穿过所述柔性材料层，以便向所述金属导体提供一个或多个开口;沉积基本上均匀的导电层;图案化所述导电层，以将所述金属导体中的至少一个导入电与一个或多个焊盘接触，每个所述焊盘包括设置在所述柔性材料上的所述导电层的一部分，以及设置在所述焊盘上的焊球。还公开了由该方法制成的装置。

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