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1. 发明申请

US20060164876A1 Multi-transistor memory cells 有权
标题翻译：多晶体管存储单元
公开(公告)号：US20060164876A1
公开(公告)日：2006-07-27
申请号：US11387490
申请日：2006-03-23
申请人： Hans-Joachim Barth , Alexander Olbrich , Martin Ostermayr , Klaus Schrufer
发明人： Hans-Joachim Barth , Alexander Olbrich , Martin Ostermayr , Klaus Schrufer
IPC分类号： G11C27/00
CPC分类号： G11C11/405 , H01L27/108 , H01L27/1104
摘要： A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.
摘要翻译：描述具有三个晶体管的存储单元和具有金属电极的电容器。多个存储器单元可以被布置在存储器单元或阵列中。集电极可以用在电容器的节省空间的实施例中。

2. 发明授权

US07440334B2 Multi-transistor memory cells 有权
标题翻译：多晶体管存储单元
公开(公告)号：US07440334B2
公开(公告)日：2008-10-21
申请号：US11387490
申请日：2006-03-23
申请人： Hans-Joachim Barth , Alexander Olbrich , Martin Ostermayr , Klaus Schrüfer
发明人： Hans-Joachim Barth , Alexander Olbrich , Martin Ostermayr , Klaus Schrüfer
IPC分类号： G11C11/34
CPC分类号： G11C11/405 , H01L27/108 , H01L27/1104
摘要： A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.
摘要翻译：描述具有三个晶体管的存储单元和具有金属电极的电容器。多个存储器单元可以被布置在存储器单元或阵列中。集电极可以用在电容器的节省空间的实施例中。

3. 发明申请

US20070034920A1 Semiconductor memory cell and corresponding method of producing same 有权
标题翻译：半导体存储单元及其相应的制造方法
公开(公告)号：US20070034920A1
公开(公告)日：2007-02-15
申请号：US11493252
申请日：2006-07-26
申请人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
发明人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
IPC分类号： H01L29/94
CPC分类号： H01L27/10888 , H01L27/108 , H01L27/1085 , H01L27/10855 , H01L27/10885 , H01L28/90
摘要： A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.
摘要翻译：半导体存储单元和制造方法提供连接到选择晶体管的存储电容器。存储电容器在至少一个用于源极或漏极区域的接触孔中形成为接触孔电容器。可以成本有效地制造这种半导体存储单元并且允许高的集成密度。

4. 发明授权

US07394682B2 Bit line dummy core-cell and method for producing a bit line dummy core-cell 有权
公开(公告)号：US07394682B2
公开(公告)日：2008-07-01
申请号：US11586176
申请日：2006-10-25
申请人： Martin Ostermayr , Christophe Chanussot , Vincent Gouin , Alexander Olbrich
发明人： Martin Ostermayr , Christophe Chanussot , Vincent Gouin , Alexander Olbrich
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.

5. 发明申请

US20080112245A1 Bit line dummy core-cell and method for producing a bit line dummy core-cell 有权
标题翻译：位线虚拟核心单元和产生位线虚拟核心单元的方法
公开(公告)号：US20080112245A1
公开(公告)日：2008-05-15
申请号：US11586176
申请日：2006-10-25
申请人： Martin Ostermayr , Christophe Chanussot , Vincent Gouin , Alexander Olbrich
发明人： Martin Ostermayr , Christophe Chanussot , Vincent Gouin , Alexander Olbrich
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A bit line dummy core-cell comprises at least a first inverter and at least a second inverter which are cross coupled to form a bistable flip-flop. The first inverter comprises a first PMOS transistor and a first NMOS transistor connected in series by means of a first internal storage node between a high reference potential and a low reference potential. The second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series by means of a second internal storage node. The source of the second PMOS transistor and the second internal storage node are connected to the low reference potential so that the first internal storage node always stores a logic high level. A first access transistor is coupled between a dummy bit line providing a self-timing signal and the first internal node storing the logical high level.
摘要翻译：位线虚拟核心单元包括交叉耦合以形成双稳态触发器的至少第一反相器和至少第二反相器。第一反相器包括通过第一内部存储节点在高参考电位和低参考电位之间串联连接的第一PMOS晶体管和第一NMOS晶体管。第二反相器包括通过第二内部存储节点串联连接的第二PMOS晶体管和第二NMOS晶体管。第二PMOS晶体管和第二内部存储节点的源极连接到低参考电位，使得第一内部存储节点总是存储逻辑高电平。第一存取晶体管耦合在提供自定时信号的伪位线和存储逻辑高电平的第一内部节点之间。

6. 发明授权

US07531420B2 Semiconductor memory cell and corresponding method of producing same 有权
标题翻译：半导体存储单元及其相应的制造方法
公开(公告)号：US07531420B2
公开(公告)日：2009-05-12
申请号：US11493252
申请日：2006-07-26
申请人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
发明人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/10888 , H01L27/108 , H01L27/1085 , H01L27/10855 , H01L27/10885 , H01L28/90
摘要： A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.
摘要翻译：半导体存储单元和制造方法提供连接到选择晶体管的存储电容器。存储电容器在至少一个用于源极或漏极区域的接触孔中形成为接触孔电容器。可以成本有效地制造这种半导体存储单元并且允许高的集成密度。

7. 发明授权

US07304342B2 Semiconductor memory cell and associated fabrication method 有权
标题翻译：半导体存储单元及相关制造方法
公开(公告)号：US07304342B2
公开(公告)日：2007-12-04
申请号：US11039745
申请日：2005-01-18
申请人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
发明人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1087 , H01L27/10835 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.
摘要翻译：提供了一种半导体存储单元和相关的制造方法，其中存储电容器连接到选择晶体管。存储电容器形成在半导体衬底的沟槽中。在沟槽表面上形成电容器电介质和导电填充层，用于实现电容器对电极。填充层具有在沟槽外延伸到漏极区域并与其电连接的突起。

8. 发明申请

US20050156218A1 Semiconductor memory cell and associated fabrication method 有权
标题翻译：半导体存储单元及相关制造方法
公开(公告)号：US20050156218A1
公开(公告)日：2005-07-21
申请号：US11039745
申请日：2005-01-18
申请人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
发明人： Thomas Nirschl , Alexander Olbrich , Martin Ostermayr
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/94
CPC分类号： H01L27/1087 , H01L27/10835 , H01L29/66181 , H01L29/945
摘要： A semiconductor memory cell and an associated fabrication method are provided in which a storage capacitor is connected to a selection transistor. The storage capacitor is formed in a trench of a semiconductor substrate. At the trench surface, a capacitor dielectric and an electrically conductive filling layer are formed thereon for realization of a capacitor counterelectrode. The filling layer has a projection that extends outside the trench as far as the drain region and is electrically connected thereto.
摘要翻译：提供了一种半导体存储单元和相关的制造方法，其中存储电容器连接到选择晶体管。存储电容器形成在半导体衬底的沟槽中。在沟槽表面上形成电容器电介质和导电填充层，用于实现电容器对电极。填充层具有在沟槽外延伸到漏极区域并与其电连接的突起。

9. 发明授权

US08853791B2 SRAM memory cell having a dogleg shaped gate electrode structure 有权
标题翻译： SRAM存储单元具有狗形栅电极结构
公开(公告)号：US08853791B2
公开(公告)日：2014-10-07
申请号：US11593290
申请日：2006-11-06
申请人： Uwe Paul Schroeder , Martin Ostermayr
发明人： Uwe Paul Schroeder , Martin Ostermayr
IPC分类号： H01L27/07 , G11C11/412 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/412
摘要： A memory cell includes diffusion regions formed in a substrate. Each of the diffusion regions extends along a vertical direction in a layout view at a substrate level. A first gate electrode structure at a gate electrode level is generally dogleg shaped. The first gate electrode structure extends in an oblique direction, turns to a horizontal direction, extends over and crosses the diffusion regions in the horizontal direction. A first contact structure at a contact level is generally rectangular shaped in the layout view of the cell. The first contact structure electrically connects a first source/drain region of the first diffusion region to the first gate electrode structure and the first source/drain region of the second diffusion region. The first contact structure extends from the first source/drain region of the first diffusion region to the first source/drain region of the second diffusion region at the contact level.
摘要翻译：存储单元包括形成在基板中的扩散区域。每个扩散区域在衬底层的布局图中沿垂直方向延伸。门电极级的第一栅极电极结构通常是狗牙形。第一栅电极结构沿倾斜方向延伸，向水平方向延伸，在水平方向上延伸并与扩散区交叉。接触级的第一接触结构在电池的布局视图中通常为矩形。第一接触结构将第一扩散区域的第一源极/漏极区域与第一扩散区域的第一栅极电极结构和第一源极/漏极区域电连接。第一接触结构从第一扩散区的第一源极/漏极区域延伸到第二扩散区域的第一源极/漏极区域处于接触电平。

10. 发明授权

US08546916B2 Capacitors and methods of manufacture thereof 有权
标题翻译：电容器及其制造方法
公开(公告)号：US08546916B2
公开(公告)日：2013-10-01
申请号：US12127576
申请日：2008-05-27
申请人： Martin Ostermayr , Richard Lindsay
发明人： Martin Ostermayr , Richard Lindsay
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/11 , H01L27/1104 , H01L29/94
摘要： Semiconductor devices, capacitors, and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a capacitor includes forming a first material over a workpiece, and patterning the first material, forming a first capacitor plate in a first region of the workpiece and forming a first element in a second region of the workpiece. A second material is formed over the workpiece and over the patterned first material. The second material is patterned, forming a capacitor dielectric and a second capacitor plate in the first region of the workpiece over the first capacitor plate and forming a second element in a third region of the workpiece.
摘要翻译：公开了半导体器件，电容器及其制造方法。在一个实施例中，制造电容器的方法包括在工件上形成第一材料，并对第一材料进行构图，在工件的第一区域中形成第一电容器板，并在工件的第二区域中形成第一元件。第二材料形成在工件上面和图案化的第一材料上。图案化第二材料，在第一电容器板上的工件的第一区域中形成电容器电介质和第二电容器板，并在工件的第三区域中形成第二元件。

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