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1. 发明申请

US20070003135A1 Reference data optimization learning method and pattern recognition system 有权
标题翻译：参考数据优化学习方法和模式识别系统
公开(公告)号：US20070003135A1
公开(公告)日：2007-01-04
申请号：US11508901
申请日：2006-08-24
申请人： Hans Mattausch , Tetsushi Koide , Yoshinori Shirakawa
发明人： Hans Mattausch , Tetsushi Koide , Yoshinori Shirakawa
IPC分类号： G06K9/62
CPC分类号： G06K9/00986 , G06K9/6272
摘要： The present invention is directed to a pattern recognition system in which new reference data to be added is efficiently learned. In the pattern recognition system, there is performed the calculation of distances equivalent to similarities between input data of a pattern search target and a plurality of reference data, and based on input data of a fixed number of times corresponding to the reference data set as a recognized winner, a gravity center thereof is calculated to optimize the reference data. Furthermore, a threshold value is changed to enlarge/reduce recognition areas, whereby erroneous recognition is prevented and a recognition rate is improved.
摘要翻译：本发明涉及一种模式识别系统，其中要被添加的新的参考数据被有效地学习。在图案识别系统中，执行与图案搜索对象的输入数据和多个参考数据之间的相似度相当的距离的计算，并且基于与参考数据集相对应的固定次数的输入数据作为计算出其重心，以优化参考数据。此外，改变阈值以放大/缩小识别区域，从而防止错误识别并提高识别率。

2. 发明授权

US07881525B2 Reference data optimization learning method and pattern recognition system 有权
标题翻译：参考数据优化学习方法和模式识别系统
公开(公告)号：US07881525B2
公开(公告)日：2011-02-01
申请号：US11508901
申请日：2006-08-24
申请人： Hans Jurgen Mattausch , Tetsushi Koide , Yoshinori Shirakawa
发明人： Hans Jurgen Mattausch , Tetsushi Koide , Yoshinori Shirakawa
IPC分类号： G06K9/00
CPC分类号： G06K9/00986 , G06K9/6272
摘要： The present invention is directed to a pattern recognition system in which new reference data to be added is efficiently learned. In the pattern recognition system, there is performed the calculation of distances equivalent to similarities between input data of a pattern search target and a plurality of reference data, and based on input data of a fixed number of times corresponding to the reference data set as a recognized winner, a gravity center thereof is calculated to optimize the reference data. Furthermore, a threshold value is changed to enlarge/reduce recognition areas, whereby erroneous recognition is prevented and a recognition rate is improved.
摘要翻译：本发明涉及一种模式识别系统，其中要被添加的新的参考数据被有效地学习。在图案识别系统中，执行与图案搜索对象的输入数据和多个参考数据之间的相似度相当的距离的计算，并且基于与参考数据集相对应的固定次数的输入数据作为计算出其重心，以优化参考数据。此外，改变阈值以放大/缩小识别区域，从而防止错误识别并提高识别率。

3. 发明申请

US20110206144A1 RECEIVER AND TRANSMISSION/RECEPTION SYSTEM 审中-公开
标题翻译：接收器和传输/接收系统
公开(公告)号：US20110206144A1
公开(公告)日：2011-08-25
申请号：US13101679
申请日：2011-05-05
申请人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira YAMAMOTO , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L27/206 , H04L1/0057 , H04L1/206 , H04L27/2332
摘要： In a wireless receiver, a “variance” of an intermediate output signal of a demodulation section is calculated by a variance calculation section, and the calculated variance is used as a signal quality indicator which indicates the degree of goodness of a receiving condition. For example, when the “variance” is small, a gain of a low-noise amplifier is reduced, or an operation clock frequency of a baseband oscillator is reduced, etc. Thus, when the receiving condition indicated by the indicator is good and sufficient performance is ensured, the performance can be slightly lowered to reduce power consumption. The “variance” is a compact indicator which can be calculated using a simple operation, and is used as a new signal quality indicator.
摘要翻译：在无线接收机中，通过方差计算部分计算出解调部分的中间输出信号的“方差”，将所计算出的方差作为表示接收条件良好程度的信号质量指标。例如，当“方差”小时，降低了低噪声放大器的增益，或降低了基带振荡器的操作时钟频率等。因此，当指示符指示的接收条件良好且足够时性能得到保证，性能可以稍微降低以降低功耗。 “方差”是可以使用简单操作计算的紧凑指示器，并且用作新的信号质量指示符。

4. 发明申请

US20110205444A1 RECEIVER, SIGNAL PROCESSING APPARATUS, AND VIDEO DISPLAY APPARATUS 有权
标题翻译：接收器，信号处理装置和视频显示装置
公开(公告)号：US20110205444A1
公开(公告)日：2011-08-25
申请号：US13101654
申请日：2011-05-05
申请人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H04N5/455
CPC分类号： H04N7/163 , G09G5/006 , G09G2330/021 , G09G2340/12 , G09G2370/12 , G09G2370/16 , G09G2370/20 , G09G2370/22 , H04N21/4305 , H04N21/43615 , H04N21/44
摘要： A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.
摘要翻译：一种用于以多个传输方案接收信号的接收机，其成功地减小了其电路尺寸。用于接收基带信号和调制信号的接收机包括：第一PLL电路，被配置为基于与基带信号同步的外部时钟产生第一内部时钟; 解调器，被配置为解调所述调制信号以输出所述解调信号; 选择器，被配置为选择所述基带信号或所述解调信号之一; 以及第一CDR电路，被配置为通过使用第一内部时钟从由选择器选择的信号中产生恢复的时钟和恢复的数据。

5. 发明申请

US20100020250A1 REPRODUCED SIGNAL PROCESSOR AND VIDEO DISPLAY 失效
标题翻译：复制信号处理器和视频显示
公开(公告)号：US20100020250A1
公开(公告)日：2010-01-28
申请号：US12526746
申请日：2007-11-01
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
IPC分类号： H04N5/66 , H04N5/95
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译：在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。结果，降低了时钟频率的变化对解码处理的响应的影响。

6. 发明授权

US06458204B1 Method of producing high-quality silicon single crystals 有权
标题翻译：生产高品质硅单晶的方法
公开(公告)号：US06458204B1
公开(公告)日：2002-10-01
申请号：US09717135
申请日：2000-11-22
申请人： Masahiko Okui , Hiroki Murakami , Kazuyuki Egashira , Makoto Ito , Hiroshi Hayakawa , Kelly Garret , Yoshinori Shirakawa
发明人： Masahiko Okui , Hiroki Murakami , Kazuyuki Egashira , Makoto Ito , Hiroshi Hayakawa , Kelly Garret , Yoshinori Shirakawa
IPC分类号： C30B1520
CPC分类号： C30B29/06 , C30B15/203 , C30B15/305
摘要： A method of producing high-quality and large-diameter single crystals by the Czochralski method is disclosed which can provide wafers with a minimized number of such grown-in defects as dislocation clusters and laser scattering tomography defects. Specifically, it is a method of producing silicon single crystals which comprises carrying out the crystal pulling while maintaining the solid-melt interface during pulling in the shape of an upward convex with the central portion of the interface being higher by at least 5 mm than the peripheral region thereof and while applying a magnetic field, and optionally in addition to the above, while maintaining the temperature gradient in the direction of axis of pulling in the peripheral region at a level lower than that in the central portion in the range of from the melting point to 1,200° C. In this case, it is desirable that the portion of the single crystal surface lying at least 50 mm above the melt surface be shielded from direct radiant heat from the heater and/or crucible wall, that a horizontal magnetic field of 0.08 to 0.3 T be applied in parallel with the melt surface or a cusped magnetic field showing an intensity of 0.02 to 0.07 T at a crucible wall site on the melt surface be applied and that the crucible be rotated at a speed of not more than 5 min−1 and the single crystal at a speed of not less than 13 min−1.
摘要翻译：公开了通过Czochralski方法生产高质量和大直径单晶的方法，其可以为晶片提供最少数量的诸如位错簇和激光散射层析成像缺陷的这种生长缺陷。具体地说，它是一种生产硅单晶的方法，其中包括在拉伸成呈向上凸起的形状的同时保持固溶体界面的同时进行晶体拉伸，其中界面的中心部分高于并且在施加磁场的同时，并且可选地除了上述之外，同时保持在周边区域中的拉动轴线方向上的温度梯度比在中心部分的温度梯度低熔点为1200℃。在这种情况下，希望在熔体表面上方至少50毫米的单晶表面的部分被屏蔽不受来自加热器和/或坩埚壁的直接辐射热，即水平磁在熔融表面上的坩埚壁部位处，与熔体表面平行施加0.08〜0.3T的场，或者表示强度为0.02〜0.07T的尖细磁场b 并且坩埚以不超过5分钟-1的速度旋转，并且单晶以不小于13分钟-1的速度旋转。

7. 发明授权

US08305493B2 Receiver, signal processing apparatus, and video display apparatus 有权
标题翻译：接收机，信号处理装置和视频显示装置
公开(公告)号：US08305493B2
公开(公告)日：2012-11-06
申请号：US13101654
申请日：2011-05-05
申请人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
发明人： Akira Yamamoto , Kouji Okamoto , Yoshinori Shirakawa
IPC分类号： H03L7/00 , H04N3/27 , H04N5/268
CPC分类号： H04N7/163 , G09G5/006 , G09G2330/021 , G09G2340/12 , G09G2370/12 , G09G2370/16 , G09G2370/20 , G09G2370/22 , H04N21/4305 , H04N21/43615 , H04N21/44
摘要： A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.
摘要翻译：一种用于以多个传输方案接收信号的接收机，其成功地减小了其电路尺寸。用于接收基带信号和调制信号的接收机包括：第一PLL电路，被配置为基于与基带信号同步的外部时钟产生第一内部时钟; 解调器，被配置为解调所述调制信号以输出所述解调信号; 选择器，被配置为选择所述基带信号或所述解调信号之一; 以及第一CDR电路，被配置为通过使用第一内部时钟从由选择器选择的信号中产生恢复的时钟和恢复的数据。

8. 发明授权

US08098972B2 Reproduced signal processor and video display 失效
标题翻译：转载信号处理器和视频显示
公开(公告)号：US08098972B2
公开(公告)日：2012-01-17
申请号：US12526746
申请日：2007-11-01
申请人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
发明人： Kouji Okamoto , Akira Yamamoto , Hiroki Mouri , Yoshinori Shirakawa
IPC分类号： H04N5/932 , H04N5/935
CPC分类号： H04L7/0331 , G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B20/14 , G11B2020/1287 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562 , H03L7/06
摘要： In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.
摘要翻译：在前馈控制型再现信号处理器中，时钟发生器1根据由数字值发生器7设定的数字值改变时钟频率。因此，优化了系统的功耗并且便于控制。此外，当频率锁定状态被建立，其中由频率比计算器3计算的频率比满足设定条件时，使用时钟发生器1的时钟产生具有小变化的调制分量。因此，数字值为用调制分量更新，使得时钟发生器1的时钟频率的变化逐渐变化。结果，降低了时钟频率的变化对解码处理的响应的影响。

9. 发明申请

US20110095786A1 PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE 审中-公开
标题翻译：相位比较器，PLL电路，信息再现处理装置，光盘播放装置和磁盘播放装置
公开(公告)号：US20110095786A1
公开(公告)日：2011-04-28
申请号：US12515337
申请日：2008-09-22
申请人： Akira Yamamoto , Yoshinori Shirakawa , Kouji Okamoto , Hiroki Mouri
发明人： Akira Yamamoto , Yoshinori Shirakawa , Kouji Okamoto , Hiroki Mouri
IPC分类号： H03D13/00
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10222 , G11B20/10425 , G11B20/14 , G11B2220/2537 , H03L7/091 , H04L7/0334
摘要： In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section 701, receiving the reproduction data, outputs a rising cross detection signal, a falling cross detection signal and three phase error candidates that are three consecutive samples. Rising and falling reference value hold sections 703 and 704 respectively output rising and falling reference values. When receiving the rising or falling cross detection signal, a phase error calculation section 702 outputs a sample the difference of which from the rising or falling reference value is minimum in absolute value, out of the three samples including a zero cross sample, as a phase error. The phase error is held in the rising or falling reference value hold section 703 or 704 as the rising or falling reference value for the next phase error calculation.
摘要翻译：在用于提取与再现数据同步的时钟的同步时钟提取电路的相位比较器中，接收再现数据的零交叉检测部分701输出上升交叉检测信号，下降交叉检测信号和三相误差候选，是连续三个样本。上升和下降参考值保持部分703和704分别输出上升和下降参考值。当接收到上升或下降的交叉检测信号时，相位误差计算部分702将包含零交叉样本的三个样本中的从上升或下降基准值的差值的绝对值的差值输出为相位错误。相位误差保持在上升或下降基准值保持部分703或704中作为下一个相位误差计算的上升或下降基准值。

10. 发明申请

US20100172629A1 REPRODUCTION SIGNAL PROCESSING DEVICE AND VIDEO DISPLAY DEVICE 审中-公开
标题翻译：生成信号处理装置和视频显示装置
公开(公告)号：US20100172629A1
公开(公告)日：2010-07-08
申请号：US12066207
申请日：2007-06-19
申请人： Yoshinori Shirakawa , Akira Yamamoto
发明人： Yoshinori Shirakawa , Akira Yamamoto
IPC分类号： H04N5/95
CPC分类号： G11B20/1403 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B20/10296 , G11B2220/2537
摘要： A reproduction signal processing device employing a fully digital timing recovery scheme, which obtains asynchronous digital data with the sampling clock of the A/D converter being asynchronous with the channel clock, wherein an A/D converter 102 converts the input analog signal to asynchronous digital data based on an asynchronous clock of a clock generator 103. A baseline controller 105 generates, at a pseudo-synchronous data generator 1051 therein, pseudo-synchronous data based on the asynchronous digital data from the A/D converter 102 and timing error information and a pseudo-synchronous clock from a timing detector 104. An the offset component calculator 1053 calculates an offset component for the pseudo-synchronous data, and subtracts the offset component at the subtractor 1050. Thus, the offset component contained in the asynchronous digital data is precisely removed.
摘要翻译：一种使用全数字定时恢复方案的再现信号处理装置，其获得异步数字数据，其中A / D转换器的采样时钟与信道时钟异步，其中A / D转换器102将输入的模拟信号转换为异步数字基于时钟发生器103的异步时钟的数据。基线控制器105在其伪同步数据发生器1051中产生基于来自A / D转换器102的异步数字数据的伪同步数据和定时误差信息，以及来自定时检测器104的伪同步时钟。偏移分量计算器1053计算伪同步数据的偏移分量，并减去减法器1050处的偏移分量。因此，包含在异步数字数据中的偏移分量是精确删除。

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