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1. 发明授权

US5008878A High-speed modular switching apparatus for circuit and packet switched traffic 失效
标题翻译：用于电路和分组交换业务的高速模块化交换设备
公开(公告)号：US5008878A
公开(公告)日：1991-04-16
申请号：US257656
申请日：1988-10-14
申请人： Hamid Ahmadi , Johannes G. Beha , Wolfgang E. Denzel , Antonius P. Engbersen , Ronald P. Luijten , Charles A. Murphy , Erich Port
发明人： Hamid Ahmadi , Johannes G. Beha , Wolfgang E. Denzel , Antonius P. Engbersen , Ronald P. Luijten , Charles A. Murphy , Erich Port
IPC分类号： H04L12/56
CPC分类号： H04L49/25 , H04L49/101 , H04L49/1523 , H04L49/254 , H04L49/3027 , H04L49/45
摘要： In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.

2. 发明授权

US5224093A High-speed multi-port FIFO buffer circuit 失效
标题翻译：高速多端口FIFO缓冲电路
公开(公告)号：US5224093A
公开(公告)日：1993-06-29
申请号：US779741
申请日：1991-10-21
申请人： Wolfgang E. Denzel , Antonius J. Engbersen
发明人： Wolfgang E. Denzel , Antonius J. Engbersen
IPC分类号： G06F12/00 , G06F5/16 , G06F13/38 , G11C7/00 , H04L12/56
CPC分类号： G06F5/16 , H04L49/3027 , H04L49/3081 , H04L2012/5681 , H04L49/503
摘要： A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on only some of the input lines (130, 230) and outputs it on adjacent output lines (140, 150, 240, 250). The data is written concurrently into consecutive memory locations in one of the two memories (160, 170, 260, 270).

3. 发明授权

US5574885A Modular buffer memory with separately controllable logical output queues for use in packet switched networks 失效
标题翻译：具有单独可控逻辑输出队列的模块化缓冲存储器，用于分组交换网络
公开(公告)号：US5574885A
公开(公告)日：1996-11-12
申请号：US341467
申请日：1994-11-17
申请人： Wolfgang E. Denzel , Antonius J. Engbersen , Gunnar Karlsson
发明人： Wolfgang E. Denzel , Antonius J. Engbersen , Gunnar Karlsson
IPC分类号： G06F13/38 , H04L12/56 , G06F13/18
CPC分类号： H04L12/56
摘要： A modular system for a buffer memory used for storing output queues (80a-k) of a packet switch is described. A series of memories (90) are each connected to both the input lines (10a-k) and the output lines (160a-k) of the switch. Each memory (90) is provided with a memory controller (100) connected to a latch (50) which is in turn connected to AND gates (60a-k). These AND gates (60a-k) ensure that packets are only stored in the memory (90) of the module in which the first latch (50) is set. When the memory (90) is full, the memory controller (100) resets this first latch (50) in the current module and sets the corresponding first latch (50) in the next module. The packets are then read into the memory (90) of the next module. A marker circuit (70) is used to insert in the output queues (80a-k) a marker to indicate that the next entries of the queue are to be found in the next module. On reading out the packets, this marker is detected by a detector (110a-k) which then resets a second latch (140a-k) in the module from which the packets are currently being read and sets a corresponding second latch (140a-k) in the next module. AND gates (150a-k) ensure that packets are only read out of those output buffer queues (80a-k) whose corresponding second latch (140a-k) is set. Each of the switch output lines (160a-k) can therefore only receive packets from one module. Different switch output lines (160a-k) will, however, receive packets from different modules.
摘要翻译：描述用于存储分组交换机的输出队列（80a-k）的用于缓冲存储器的模块化系统。一系列存储器（90）分别连接到开关的输入线（10a-k）和输出线（160a-k）。每个存储器（90）设置有连接到锁存器（50）的存储器控制器（100），锁存器又连接到与门（60a-k）。这些与门（60a-k）确保分组仅存储在设置有第一锁存器（50）的模块的存储器（90）中。当存储器（90）满时，存储器控制器（100）将当前模块中的该第一锁存器（50）复位，并将相应的第一锁存器（50）设置在下一个模块中。然后将数据包读入下一个模块的存储器（90）。标记电路（70）用于在输出队列（80a-k）中插入一个标记，以指示在下一个模块中找到队列的下一个条目。在读出分组时，该标记由检测器（110a-k）检测，其然后复位当前正在读取分组的模块中的第二锁存器（140a-k），并设置相应的第二锁存器（140a-k））在下一个模块。与门（150a-k）确保分组仅从其对应的第二锁存器（140a-k）被设置的那些输出缓冲器队列（80a-k）中读出。因此，每个开关输出线（160a-k）只能从一个模块接收分组。然而，不同的开关输出线（160a-k）将接收来自不同模块的分组。

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