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1. 发明授权

US08130581B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08130581B2
公开(公告)日：2012-03-06
申请号：US12926096
申请日：2010-10-26
申请人： Hajime Sato , Masao Shinozaki
发明人： Hajime Sato , Masao Shinozaki
IPC分类号： G11C7/02
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C11/4087 , G11C11/4093 , G11C11/4097
摘要： The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.
摘要翻译：本发明提供一种半导体存储器件，其中通过增加连接到一对公共写入数据线的位线对的数量来减少写入放大器的数量。此外，通过减少连接到一对公共读取数据线的位线对的数量，减少连接到一对公共读取数据线的寄生电容，并且因此减小了该对公共读取数据之间的电位差线条增加缩短。因此，在防止芯片布局区域扩大的同时，可以缩短读取时间。

2. 发明授权

US07656733B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07656733B2
公开(公告)日：2010-02-02
申请号：US12059220
申请日：2008-03-31
申请人： Masao Shinozaki , Hajime Sato
发明人： Masao Shinozaki , Hajime Sato
IPC分类号： G11C7/02
CPC分类号： G11C7/22 , G11C7/227 , G11C11/412 , G11C11/419 , G11C2207/229
摘要： This invention provides a semiconductor memory device with enhanced speed performance or enabling timing adjustment reflected in characteristic variation of memory cells, adapted to suppress an increase in the number of circuit elements. A write dummy bit section comprises a first dummy line and a second dummy line corresponding to complementary bit lines and a plurality of first dummy cells formed to be similar in shape to static memory cells, wherein a write current path is coupled between the first dummy line and the second dummy line. In the write dummy bit section, one voltage level is input to the first dummy line through driver MOSFETs in relation to write signal inputs to the static memory cells and a signal change in the second dummy line precharged at the other voltage level is sensed and output. A timing control circuit deselects a word line selected by an output signal from the write dummy bit section.
摘要翻译：本发明提供了一种半导体存储器件，其具有增强的速度性能或能够反映在存储器单元的特性变化中的时序调整，适于抑制电路元件数量的增加。写入虚拟位部分包括对应于互补位线的第一虚拟线和第二虚拟线以及形状与静态存储单元类似的多个第一虚拟单元，其中写入电流路径耦合在第一虚拟线和第二虚线。在写入虚拟位部分中，相对于静态存储器单元的写信号输入，通过驱动器MOSFET将一个电压电平输入到第一虚拟线，并且在另一电压电平处预充电的第二虚拟线中的信号变化被感测和输出。定时控制电路取消由写入虚拟位部分的输出信号选择的字线。

3. 发明申请

US20070019457A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070019457A1
公开(公告)日：2007-01-25
申请号：US11452232
申请日：2006-06-14
申请人： Hajime Sato , Masao Shinozaki
发明人： Hajime Sato , Masao Shinozaki
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C11/4087 , G11C11/4093 , G11C11/4097
摘要： The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.
摘要翻译：本发明提供一种半导体存储器件，其中通过增加连接到一对公共写入数据线的位线对的数量来减少写入放大器的数量。此外，通过减少连接到一对公共读取数据线的位线对的数量，减少连接到该对公共读取数据线的寄生电容，并且因此减小了该对公共读取数据之间的电位差线条增加缩短。因此，在防止芯片布局区域扩大的同时，可以缩短读取时间。

4. 发明授权

US08351283B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08351283B2
公开(公告)日：2013-01-08
申请号：US12814478
申请日：2010-06-13
申请人： Masao Shinozaki , Hajime Sato
发明人： Masao Shinozaki , Hajime Sato
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2272
摘要： The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first DLL circuit generates a first internal clock signal so as to reduce a phase difference between a first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit. The second DLL circuit generates the second internal clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit. With the configuration, input setup and hold time can be shortened, and the frequency of the clock signal can be further increased.
摘要翻译：本发明旨在实现采用QDR方法的半导体存储装置的高速操作和低延迟。提供存储单元阵列，第一缓冲器，第二缓冲器，第一电路，第二电路，第一DLL电路和第二DLL电路。第一DLL电路产生第一内部时钟信号，以便减少经由第一缓冲器取得的第一时钟信号和发送到第一电路的第一内部时钟信号之间的相位差。第二DLL电路产生第二内部时钟信号，以便减小经由第二缓冲器取得的第二时钟信号和发送到第二电路的第二内部时钟信号之间的相位差。通过该配置，可以缩短输入建立和保持时间，并且可以进一步增加时钟信号的频率。

5. 发明申请

US20100322022A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100322022A1
公开(公告)日：2010-12-23
申请号：US12814478
申请日：2010-06-13
申请人： Masao Shinozaki , Hajime Sato
发明人： Masao Shinozaki , Hajime Sato
IPC分类号： G11C8/18 , G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2272
摘要： The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first DLL circuit generates a first internal clock signal so as to reduce a phase difference between a first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit. The second DLL circuit generates the second internal clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit. With the configuration, input setup and hold time can be shortened, and the frequency of the clock signal can be further increased.
摘要翻译：本发明旨在实现采用QDR方法的半导体存储装置的高速操作和低延迟。提供存储单元阵列，第一缓冲器，第二缓冲器，第一电路，第二电路，第一DLL电路和第二DLL电路。第一DLL电路产生第一内部时钟信号，以便减少经由第一缓冲器取得的第一时钟信号和发送到第一电路的第一内部时钟信号之间的相位差。第二DLL电路产生第二内部时钟信号，以便减小经由第二缓冲器取得的第二时钟信号和发送到第二电路的第二内部时钟信号之间的相位差。通过该配置，可以缩短输入建立和保持时间，并且可以进一步增加时钟信号的频率。

6. 发明授权

US07440355B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07440355B2
公开(公告)日：2008-10-21
申请号：US11452232
申请日：2006-06-14
申请人： Hajime Sato , Masao Shinozaki
发明人： Hajime Sato , Masao Shinozaki
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C11/4087 , G11C11/4093 , G11C11/4097
摘要： The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.
摘要翻译：本发明提供一种半导体存储器件，其中通过增加连接到一对公共写入数据线的位线对的数量来减少写入放大器的数量。此外，通过减少连接到一对公共读取数据线的位线对的数量，减少连接到该对公共读取数据线的寄生电容，并且因此减小了该对公共读取数据之间的电位差线条增加缩短。因此，在防止芯片布局区域扩大的同时，可以缩短读取时间。

7. 发明申请

US20110044095A1 Semiconductor memory device 有权
公开(公告)号：US20110044095A1
公开(公告)日：2011-02-24
申请号：US12926096
申请日：2010-10-26
申请人： Hajime Sato , Masao Shinozaki
发明人： Hajime Sato , Masao Shinozaki
IPC分类号： G11C11/413
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C11/4087 , G11C11/4093 , G11C11/4097
摘要： The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.

8. 发明授权

US07903490B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07903490B2
公开(公告)日：2011-03-08
申请号：US12232369
申请日：2008-09-16
申请人： Hajime Sato , Masao Shinozaki
发明人： Hajime Sato , Masao Shinozaki
IPC分类号： G11C7/02
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C11/4087 , G11C11/4093 , G11C11/4097
摘要： The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.
摘要翻译：本发明提供一种半导体存储器件，其中通过增加连接到一对公共写入数据线的位线对的数量来减少写入放大器的数量。此外，通过减少连接到一对公共读取数据线的位线对的数量，减少连接到该对公共读取数据线的寄生电容，并且因此减小了该对公共读取数据之间的电位差线条增加缩短。因此，在防止芯片布局区域扩大的同时，可以缩短读取时间。

9. 发明申请

US20090027986A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20090027986A1
公开(公告)日：2009-01-29
申请号：US12232369
申请日：2008-09-16
申请人： Hajime Sato , Masao Shinozaki
发明人： Hajime Sato , Masao Shinozaki
IPC分类号： G11C7/06
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C11/4087 , G11C11/4093 , G11C11/4097
摘要： The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.
摘要翻译：本发明提供一种半导体存储器件，其中通过增加连接到一对公共写入数据线的位线对的数量来减少写入放大器的数量。此外，通过减少连接到一对公共读取数据线的位线对的数量，减少连接到该对公共读取数据线的寄生电容，并且因此减小了该对公共读取数据之间的电位差线条增加缩短。因此，在防止芯片布局区域扩大的同时，可以缩短读取时间。

10. 发明授权

US08951739B2 Biomarker for depression, method for measuring a biomarker for depression, computer program, and recording medium 有权
标题翻译：用于抑郁症的生物标志物，用于抑制抑制的生物标志物的测定方法，计算机程序和记录介质
公开(公告)号：US08951739B2
公开(公告)日：2015-02-10
申请号：US13389903
申请日：2010-08-12
申请人： Noriyuki Kawamura , Kosaku Shinoda , Yoshiaki Ohashi , Takamasa Ishikawa , Hajime Sato
发明人： Noriyuki Kawamura , Kosaku Shinoda , Yoshiaki Ohashi , Takamasa Ishikawa , Hajime Sato
IPC分类号： G01N33/53 , G01N33/68
CPC分类号： G01N33/6893 , G01N33/92 , G01N2800/304 , G01N2800/52 , Y10T436/163333
摘要： Provided is a method for using low molecular weight compounds found in the body as a biomarker for diagnosing depression. Specifically, more than one compound selected from a group comprising the following are used: ADP-ribose, ATP, ADP, AMP, serotonin, tryptophan, kynurenine, SDMA (symmetrical dimethylarginine), threonine, glyceric acid, serine, N-acetylaspartic acid, glutamic acid, trigonelline, creatine, 2-methylserine, sphingosine, homovanillic acid, piperidine, sulfoxidized methionine, pipecolic acid, sphinganine, gamma-butyrobetaine, guanidinoacetic acid, isobutyric acid, creatinine, sarcosine, 3-methylbutyric acid, nicotinamide, betaine, ornithine, carnitine, ethanolamine, phosphoethanolamine, taurine, hypotaurine, aspartic acid, methionine, and tyrosine.
摘要翻译：提供了一种使用体内发现的低分子化合物作为诊断抑郁症的生物标志物的方法。具体地说，使用选自以下的多种化合物：ADP-核糖，ATP，ADP，AMP，5-羟色胺，色氨酸，犬尿胆碱，SDMA（对称二甲基精氨酸），苏氨酸，甘油酸，丝氨酸，N-乙酰天冬氨酸，谷氨酸，葫芦巴碱，肌酸，2-甲基丝氨酸，鞘氨醇，高香草酸，哌啶，亚砜化甲硫氨酸，哌可酸，二氢鞘氨酸，γ-丁基甜菜碱，胍基乙酸，异丁酸，肌氨酸，肌氨酸，3-甲基丁酸，烟酰胺，甜菜碱，鸟氨酸肉碱，乙醇胺，磷酸乙醇胺，牛磺酸，牛磺酸，天门冬氨酸，甲硫氨酸和酪氨酸。

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