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1. 发明授权

US07202156B2 Process for manufacturing a wiring substrate 有权
标题翻译：制造布线基板的工艺
公开(公告)号：US07202156B2
公开(公告)日：2007-04-10
申请号：US10989515
申请日：2004-11-17
申请人： Hajime Saiki , Atsuhiko Sugimoto , Mikiya Sakurai
发明人： Hajime Saiki , Atsuhiko Sugimoto , Mikiya Sakurai
IPC分类号： H01L21/4763
CPC分类号： H05K3/4661 , H05K3/108 , H05K3/181 , H05K3/4602 , H05K2201/0209
摘要： A process for manufacturing a wiring substrate, comprising: a step of forming an insulating resin layer containing an inorganic filler over a wiring layer formed on at least one surface of an insulating substrate; a step of forming a thin copper film layer by roughening a surface of the insulating resin layer and plating the same electrolessly with copper; a step of forming an insulating film over the thin copper film layer; a step of forming plated resists profiling a pattern by exposing and developing the insulating film with the pattern; and a step of forming wiring pattern layers by an electrolytic copper plating on a surface of the insulating resin layer having the plated resists formed thereon, wherein at least one of the plated resists has a width of less than 20 μm, and the plated resists include adjoining plated resists in which a clearance between said adjoining plated resists has a width of less than 20 μm.
摘要翻译：一种布线基板的制造方法，包括：在绝缘基板的至少一个面上形成的布线层上形成含有无机填料的绝缘树脂层的工序; 通过使绝缘树脂层的表面粗糙化并用铜电化而使其形成薄铜膜层的步骤; 在所述薄铜膜层上形成绝缘膜的步骤; 通过用图案曝光和显影绝缘膜来形成电镀抗蚀剂的步骤; 以及在其上形成有电镀抗蚀剂的绝缘树脂层的表面上通过电解铜电镀形成布线图案层的步骤，其中至少一个电镀抗蚀剂具有小于20μm的宽度，并且电镀抗蚀剂包括邻接的电镀抗蚀剂，其中所述相邻的电镀抗蚀剂之间的间隙具有小于20μm的宽度。

2. 发明申请

US20050106854A1 Process for manufacturing a wiring substrate 有权
标题翻译：制造布线基板的工艺
公开(公告)号：US20050106854A1
公开(公告)日：2005-05-19
申请号：US10989515
申请日：2004-11-17
申请人： Hajime Saiki , Atsuhiko Sugimoto , Mikiya Sakurai
发明人： Hajime Saiki , Atsuhiko Sugimoto , Mikiya Sakurai
IPC分类号： H05K3/18 , H05K3/10 , H05K3/46 , H05K1/11 , H01L21/4763 , H01R12/04
CPC分类号： H05K3/4661 , H05K3/108 , H05K3/181 , H05K3/4602 , H05K2201/0209
摘要： A process for manufacturing a wiring substrate, comprising: a step of forming an insulating resin layer containing an inorganic filler over a wiring layer formed on at least one surface of an insulating substrate; a step of forming a thin copper film layer by roughening a surface of the insulating resin layer and plating the same electrolessly with copper; a step of forming an insulating film over the thin copper film layer; a step of forming plated resists profiling a pattern by exposing and developing the insulating film with the pattern; and a step of forming wiring pattern layers by an electrolytic copper plating on a surface of the insulating resin layer having the plated resists formed thereon, wherein at least one of the plated resists has a width of less than 20 μm, and -the plated resists include adjoining plated resists in which a clearance between said adjoining plated resists has a width of less than 20 μm.
摘要翻译：一种布线基板的制造方法，包括：在绝缘基板的至少一个面上形成的布线层上形成含有无机填料的绝缘树脂层的工序; 通过使绝缘树脂层的表面粗糙化并用铜电化而使其形成薄铜膜层的步骤; 在所述薄铜膜层上形成绝缘膜的步骤; 通过利用图案曝光和显影绝缘膜来形成电镀抗蚀剂成型图案的步骤; 以及在其上形成有电镀抗蚀剂的绝缘树脂层的表面上通过电解铜电镀形成布线图案层的步骤，其中至少一个电镀抗蚀剂具有小于20μm的宽度，并且电镀抗蚀剂包括邻接的电镀抗蚀剂，其中所述邻接的电镀抗蚀剂之间的间隙具有小于20μm的宽度。

3. 发明授权

US08319111B2 Wiring board having wiring laminate portion with via conductors embedded in resin insulating layers 有权
标题翻译：具有布线层叠部分的布线板，其中通孔导体嵌入在树脂绝缘层中
公开(公告)号：US08319111B2
公开(公告)日：2012-11-27
申请号：US11865919
申请日：2007-10-02
申请人： Hajime Saiki , Mikiya Sakurai , Atsuhiko Sugimoto
发明人： Hajime Saiki , Mikiya Sakurai , Atsuhiko Sugimoto
IPC分类号： H05K1/03
CPC分类号： H05K1/115 , H01L23/49827 , H01L23/49833 , H01L2924/0002 , H05K1/0271 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K2201/0209 , H05K2201/068 , H05K2201/09481 , H05K2201/0959 , H05K2201/096 , H05K2201/09627 , H05K2201/09709 , H05K2203/0733 , H01L2924/00
摘要： A wiring board having a favorable electrical reliability and in which a crack is unlikely to occur at a connection interface of via conductors even though the number of via conductors in series, which constitutes the stacked via, becomes larger than that of a conventional wiring board.
摘要翻译：即使构成堆叠通孔的串联的通孔导体的数量变得比常规的布线板大，因此具有良好的电气可靠性并且在通孔导体的连接界面处不可能发生裂纹的布线板。

4. 发明申请

US20080083560A1 WIRING BOARD 有权
标题翻译：接线板
公开(公告)号：US20080083560A1
公开(公告)日：2008-04-10
申请号：US11865919
申请日：2007-10-02
申请人： Hajime Saiki , Mikiya Sakurai , Atsuhiko Sugimoto
发明人： Hajime Saiki , Mikiya Sakurai , Atsuhiko Sugimoto
IPC分类号： H05K1/03
CPC分类号： H05K1/115 , H01L23/49827 , H01L23/49833 , H01L2924/0002 , H05K1/0271 , H05K1/0366 , H05K1/0373 , H05K3/4602 , H05K2201/0209 , H05K2201/068 , H05K2201/09481 , H05K2201/0959 , H05K2201/096 , H05K2201/09627 , H05K2201/09709 , H05K2203/0733 , H01L2924/00
摘要： A wiring board having a favorable electrical reliability and in which a crack is unlikely to occur at a connection interface of via conductors even though the number of via conductors in series, which constitutes the stacked via, becomes larger than that of a conventional wiring board.
摘要翻译：即使构成堆叠通孔的串联的通孔导体的数量变得比常规的布线板大，因此具有良好的电气可靠性并且在通孔导体的连接界面处不可能发生裂纹的布线板。

5. 发明申请

US20050103520A1 Wiring substrate and manufacturing process of the same 有权
标题翻译：接线基板和制造工艺相同
公开(公告)号：US20050103520A1
公开(公告)日：2005-05-19
申请号：US10989517
申请日：2004-11-17
申请人： Hajime Saiki , Mikiya Sakurai
发明人： Hajime Saiki , Mikiya Sakurai
IPC分类号： H05K3/00 , H05K3/46 , H05K1/00
CPC分类号： H05K3/0035 , H05K3/4602 , H05K3/4661 , H05K2201/0209 , Y10T29/49156
摘要： A wiring substrate comprising: a lower insulating resin layer; wiring pattern layers provided on surfaces of the lower insulating resin layer; upper insulating resin layers provided on surfaces of the lower insulating resin layer and the wiring pattern layers; via holes extending through at least one of the upper insulating resin layers; and via conductors provided in the via holes and connected electrically with at least one of the wiring pattern layers, wherein at least one of the upper insulating resin layers contains an epoxy resin containing 30 to 50% by weigh of an inorganic filler of SiO2 having an average grain diameter of 1.0 to 10.0 μm, and at least one of the via holes has a lower end opening diameter of 40 μm or more and less than 60 μm on a side of the wiring pattern layers.
摘要翻译：一种布线基板，包括：下绝缘树脂层; 布线图案层设置在下绝缘树脂层的表面上; 设置在下绝缘树脂层和布线图案层的表面上的上绝缘树脂层; 通孔延伸穿过上绝缘树脂层中的至少一个; 以及通孔，其设置在所述通孔中，并且与至少一个所述布线图案层电连接，其中所述上绝缘树脂层中的至少一个包含含有30至50重量％的SiO

6. 发明授权

US08937256B2 Method for manufacturing wiring board for mounting electronic component, wiring board for mounting electronic component, and method for manufacturing wiring board having an electronic component 有权
标题翻译：用于制造电子部件安装用布线板的方法，电子部件安装用布线板以及具有电子部件的布线基板的制造方法
公开(公告)号：US08937256B2
公开(公告)日：2015-01-20
申请号：US13353965
申请日：2012-01-19
申请人： Masahiro Inoue , Hajime Saiki , Atsuhiko Sugimoto
发明人： Masahiro Inoue , Hajime Saiki , Atsuhiko Sugimoto
IPC分类号： H01K1/02 , H05K13/04 , H05K3/34 , H01L23/00
CPC分类号： H05K3/3478 , H01L24/81 , H01L2224/10126 , H01L2224/16225 , H01L2924/14 , H05K3/3436 , H05K3/3484 , H05K2201/10977 , H01L2924/00
摘要： A method for manufacturing a wiring board for mounting an electronic component, a wiring board for mounting an electronic component, and a method for manufacturing an electronic-component-mounted wiring board are provided. A bonding material paste, which can include solder and an electric insulation material made of a resin, can be placed on chip mount terminal pads and heated to fuse the solder and soften the electric insulation material. Subsequently, the solder is solidified to form solder bumps. Further, the electric insulation material is cured on a surface of each of the solder bumps and a surface of a multilayer board around each of the solder bumps to form an electric insulation surface layer. Accordingly, when a chip is mounted to such wiring boards, the electric insulation surface layer minimizes or eliminates the connection between adjacent solder bumps during re-fusing of the solder.
摘要翻译：本发明提供一种电子部件安装用布线基板的制造方法，电子部件的安装用布线基板以及电子元件搭载布线基板的制造方法。可以将包括焊料和由树脂制成的电绝缘材料的接合材料糊料放置在芯片安装端子焊盘上并加热以熔化焊料并软化电绝缘材料。随后，焊料固化形成焊料凸块。此外，电绝缘材料在每个焊料凸块的表面和每个焊料凸块周围的多层板的表面上固化，以形成电绝缘表面层。因此，当芯片安装到这种布线板时，电绝缘表面层在焊料的再熔合期间使相邻焊料凸块之间的连接最小化或消除。

7. 发明授权

US07692103B2 Wiring substrate and manufacturing process of the same 有权
标题翻译：接线基板和制造工艺相同
公开(公告)号：US07692103B2
公开(公告)日：2010-04-06
申请号：US10989517
申请日：2004-11-17
申请人： Hajime Saiki , Mikiya Sakurai
发明人： Hajime Saiki , Mikiya Sakurai
IPC分类号： H01R12/04 , H05K1/11 , H05K3/02
CPC分类号： H05K3/0035 , H05K3/4602 , H05K3/4661 , H05K2201/0209 , Y10T29/49156
摘要： A wiring substrate includes a lower insulating resin layer; wiring pattern layers provided on surfaces of the lower insulating resin layer; upper insulating resin layers; and via holes and via conductors connected electrically with at least one of the wiring pattern layers. An upper insulating resin layer includes an epoxy resin containing 30 to 50% by weight of an inorganic filler of SiO2 having an average grain diameter of 1.0 to 10.0 μm, and a via having a lower end opening diameter of between 40 μm and 60 μm.
摘要翻译：布线基板包括下绝缘树脂层; 布线图案层设置在下绝缘树脂层的表面上; 上绝缘树脂层; 以及与至少一个布线图案层电连接的通孔和通孔导体。上部绝缘树脂层包括含有30〜50重量％的平均粒径为1.0〜10.0μm的SiO 2的无机填料的环氧树脂，以及下端开口直径为40μm〜60μm的通孔。

8. 发明授权

US09132494B2 Wiring board and method for manufacturing the same 有权
标题翻译：接线板及其制造方法
公开(公告)号：US09132494B2
公开(公告)日：2015-09-15
申请号：US13354043
申请日：2012-01-19
申请人： Masahiro Inoue , Hajime Saiki , Atsuhiko Sugimoto
发明人： Masahiro Inoue , Hajime Saiki , Atsuhiko Sugimoto
IPC分类号： H05K1/11 , B23K1/00 , B23K35/26 , B23K35/22 , C22C11/06 , C22C13/00 , H01L23/00 , H01L23/498 , H01L21/48 , H01L21/683 , H05K3/46
CPC分类号： B23K1/00 , B23K35/22 , B23K35/26 , C22C11/06 , C22C13/00 , H01L21/4853 , H01L21/6835 , H01L23/49811 , H01L23/49822 , H01L24/00 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2221/68318 , H01L2221/68331 , H01L2221/68345 , H01L2221/68386 , H01L2224/131 , H01L2224/16237 , H01L2224/81192 , H01L2224/814 , H01L2924/15174 , H01L2924/15312 , H05K3/4682 , H05K2201/10318 , H01L2924/014
摘要： A wiring board and a method for manufacturing the wiring board reinforced by means of a resin is provided. Embodiments of the wiring board allow for reliable attachment of a connection member, like a socket, to a terminal member. For example, a base of terminal pins is put on pin grid array (PGA) terminal pads, and a bonding material paste including solder and an electric insulation material made of a resin is placed on each of the PGA terminal pads. The bonding material paste is then heated to fuse the solder and soften the electric insulation material. Subsequently, the bonding material paste is cooled to solidify the solder and bond each of the bases to a corresponding PGA terminal pad and form an electric insulation surface layer on an exposed surface of each of solder junctions to which the respective bases are bonded.
摘要翻译：提供了一种通过树脂加强的布线板和制造布线板的方法。布线板的实施例允许将连接构件（如插座）可靠地附接到端子构件。例如，将端子引脚的基座放置在引脚格栅阵列（PGA）端子焊盘上，并且将包含焊料的接合材料浆料和由树脂制成的电绝缘材料放置在每个PGA端子焊盘上。然后将接合材料浆料加热以熔化焊料并软化电绝缘材料。随后，将接合材料浆料冷却以固化焊料，并将每个基底结合到相应的PGA端子焊盘上，并在各个基底所接合的每个焊接点的暴露表面上形成电绝缘表面层。

9. 发明授权

US09119333B2 Multilayer wiring board 有权
标题翻译：多层接线板
公开(公告)号：US09119333B2
公开(公告)日：2015-08-25
申请号：US13399547
申请日：2012-02-17
申请人： Takuya Hando , Masahiro Inoue , Hajime Saiki , Atsuhiko Sugimoto , Hidetoshi Wada
发明人： Takuya Hando , Masahiro Inoue , Hajime Saiki , Atsuhiko Sugimoto , Hidetoshi Wada
IPC分类号： H05K3/40 , H01L23/498 , H01L23/00 , H01L21/683 , H05K3/46 , H05K3/00
CPC分类号： H05K3/4007 , H01L21/6835 , H01L23/49816 , H01L23/49822 , H01L24/16 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/81192 , H01L2924/01084 , H05K3/0097 , H05K3/4682 , H05K2201/0367
摘要： A multilayer wiring board including a build-up layer, formed from one or more conductor and resin insulation layers that are layered one on top of the other, having conductive pads formed on a surface of at least one resin insulation layer so as to project from the surface are provided. The conductive pads may each include a columnar portion situated at a lower part thereof and a convex portion situated at a higher part thereof, wherein a surface of the convex portion may assume a continual curved shape. A solder layer may be formed over an upper surface of the conductive pads. Certain embodiments make it possible to minimize or eliminate the concentration of stress on the conductive pads, and may inhibit the occurrence of defective connections to a semiconductor element and infliction of damage to the conductive pads.
摘要翻译：一种多层布线基板，包括由一层或多层导体和树脂绝缘层形成的堆积层，所述导体和树脂绝缘层层叠在另一层之上，具有形成在至少一层树脂绝缘层的表面上的导电焊盘，以便从提供表面。导电垫可以各自包括位于其下部的柱状部分和位于其较高部分的凸部，其中凸部的表面可以呈现连续的弯曲形状。可以在导电焊盘的上表面上形成焊料层。某些实施例使得可以最小化或消除导电焊盘上的应力集中，并且可以抑制对半导体元件的不良连接的发生以及对导电焊盘的损坏。

10. 发明申请

US20050253263A1 Wiring substrate and process for manufacturing the same 有权
标题翻译：接线基板及其制造方法
公开(公告)号：US20050253263A1
公开(公告)日：2005-11-17
申请号：US11071203
申请日：2005-03-04
申请人： Atsuhiko Sugimoto , Hajime Saiki
发明人： Atsuhiko Sugimoto , Hajime Saiki
IPC分类号： H01L21/44 , H01L21/48 , H01L23/48 , H01L23/498 , H05K1/11 , H05K3/10 , H05K3/24 , H05K3/34
CPC分类号： H05K3/244 , H01L21/4846 , H01L23/498 , H01L23/49816 , H01L2924/0002 , H05K3/3457 , H01L2924/00
摘要： A wiring substrate incorporating nickel-plated copper terminal pads for solder bumps, wherein a nickel plating layer constituting the nickel plated copper terminal pads has a phosphorus content of 8.5 to 15.0% by mass and is covered with a gold plating layer.
摘要翻译：包括用于焊料凸块的镀镍铜端子焊盘的布线基板，其中构成镀镍铜端子焊盘的镀镍层的磷含量为8.5〜15.0质量％，被镀金层覆盖。

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