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1. 发明授权

US06307232B1 Semiconductor device having lateral high breakdown voltage element 失效
标题翻译：具有横向高击穿电压元件的半导体器件
公开(公告)号：US06307232B1
公开(公告)日：2001-10-23
申请号：US08977622
申请日：1997-11-25
申请人： Hajime Akiyama , Yoichiro Tarui
发明人： Hajime Akiyama , Yoichiro Tarui
IPC分类号： H01L2701
CPC分类号： H01L29/404 , H01L21/8258 , H01L21/84 , H01L27/1203 , H01L29/1608 , H01L29/408 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A diode having a p+ semiconductor region, an n− drift region and an n+ semiconductor region is formed in an SOI layer. An SiC layer is formed in the bottom surface of a semiconductor layer. Further, a capacitive coupled multiple field plate including conductive layers is formed between cathode and anode electrodes. As a result, a semiconductor device with a lateral high breakdown voltage element having extremely high breakdown voltage which is never restricted by electric field concentration in the surface of the SOI layer can be achieved.
摘要翻译：在SOI层中形成具有p +半导体区域，n-漂移区域和n +半导体区域的二极管。在半导体层的底面形成SiC层。此外，在阴极和阳极之间形成包括导电层的电容耦合多场板。结果，可以实现具有非常高的击穿电压的横向高击穿电压元件的半导体器件，其绝不受SOI层表面中的电场浓度的限制。

2. 发明授权

US08685848B2 Manufacturing method of silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08685848B2
公开(公告)日：2014-04-01
申请号：US13355710
申请日：2012-01-23
申请人： Yoshinori Matsuno , Yoichiro Tarui
发明人： Yoshinori Matsuno , Yoichiro Tarui
IPC分类号： H01L21/329
CPC分类号： H01L29/1608 , H01L21/0465 , H01L21/0485 , H01L29/0615 , H01L29/0619 , H01L29/6606 , H01L29/872
摘要： A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
摘要翻译：通过干热氧化在外延层上形成氧化硅膜，在SiC衬底的背面上形成欧姆电极，在SiC衬底的欧姆电极和背面之间形成欧姆接头，退火SiC 衬底，除去氧化硅膜，在外延层上形成肖特基电极。然后，进行烧结处理以在肖特基电极和外延层之间形成肖特基结。

3. 发明授权

US08115211B2 Silicon carbide semiconductor device and manufacturing method thereof 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US08115211B2
公开(公告)日：2012-02-14
申请号：US12621963
申请日：2009-11-19
申请人： Yoichiro Tarui
发明人： Yoichiro Tarui
IPC分类号： H01L31/0312 , H01L31/0256 , H01L29/74 , H01L29/76 , H01L29/94
CPC分类号： H01L21/0455 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/66068
摘要： An objective is to provide a manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the manufacturing method increase of the manufacturing cost can also be prevented as much as possible. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch
摘要翻译：目的是提供一种碳化硅半导体器件的制造方法，其中施加到栅极氧化膜的电场可以被放宽，从而可以确保可靠性，并且通过制造方法也可以防止制造成本的增加，因为尽可能的形成阱区域，沟道区域和栅电极，使得相对于源极区域的内侧的阱区域，沟道区域和栅极电极的延伸长度为Lwell，Lch和 Lg分别满足Lch

4. 发明申请

US20110195563A1 METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20110195563A1
公开(公告)日：2011-08-11
申请号：US12899061
申请日：2010-10-06
申请人： Koji Okuno , Yoichiro Tarui
发明人： Koji Okuno , Yoichiro Tarui
IPC分类号： H01L21/22
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/0615 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/7395 , H01L29/7811 , H01L29/872
摘要： A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks.
摘要翻译：根据本发明的制造碳化硅半导体器件的方法包括以下步骤：（a）在碳化硅半导体层上形成由多个单位掩模构成的注入掩模，以及（b）在硅中注入预定的离子通过使用注入掩模在预定的注入能量下形成碳化物半导体层。在步骤（a）中，形成注入掩模，使得从单位掩模中的任何点到单位掩模的末端的长度可以等于或小于当将预定离子注入到碳化硅中时获得的散射长度在预定的注入能量和注入掩模可以具有在单位掩模的尺寸和排列间隔方面彼此不同的多个区域。

5. 发明授权

US07285465B2 Method of manufacturing a SiC vertical MOSFET 有权
标题翻译：制造SiC垂直MOSFET的方法
公开(公告)号：US07285465B2
公开(公告)日：2007-10-23
申请号：US11353992
申请日：2006-02-15
申请人： Yoichiro Tarui , Ken-ichi Ohtsuka , Masayuki Imaizumi , Hiroshi Sugimoto , Tetsuya Takami
发明人： Yoichiro Tarui , Ken-ichi Ohtsuka , Masayuki Imaizumi , Hiroshi Sugimoto , Tetsuya Takami
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L21/0465 , H01L21/047 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.
摘要翻译：提供了一种半导体器件及其制造方法，其中改善了沟道电阻和JFET电阻之间的折衷关系，从而改善了器件的小型化，并且通过离子注入使用相同的掩模形成源极区域和基极区域。在使用SiC的垂直MOSFET中，通过使用相同的锥形掩模的离子注入形成源极区域和基极区域，以使基极区域呈锥形。当锥形掩模的材料与离子注入中的SiC具有相同的范围时，锥形掩模的锥角设定为30°至60°，当锥形掩模的材料为SiO 2 。

6. 发明授权

US09362391B2 Silicon carbide semiconductor device and method of manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US09362391B2
公开(公告)日：2016-06-07
申请号：US14240017
申请日：2011-09-21
申请人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
发明人： Yoichiro Tarui , Eisuke Suekawa , Naoki Yutani , Shiro Hino , Naruhisa Miura , Masayuki Imaizumi
IPC分类号： H01L29/78 , H01L29/66 , H01L29/08 , H01L29/16 , H01L21/04 , H01L21/02
CPC分类号： H01L29/78 , H01L21/02529 , H01L21/046 , H01L21/0485 , H01L29/086 , H01L29/1608 , H01L29/66068 , H01L29/66477 , H01L29/7802
摘要： It is expected that both reduction of the resistance of a source region and reduction of a leakage current in a gate oxide film be achieved in an MOSFET in a silicon carbide semiconductor device. A leakage current to occur in a gate oxide film of the MOSFET is suppressed by reducing roughness at an interface between a source region and the gate oxide film. If an impurity concentration is to become high at a surface portion of the source region, the gate oxide film is formed by dry oxidation or CVD process. If the gate oxide film is formed by wet oxidation, the impurity concentration at the surface portion of the source region is controlled at a low level.
摘要翻译：期望在碳化硅半导体器件中的MOSFET中实现源极区域的电阻降低和栅极氧化膜中的漏电流的减小。通过减少源极区域和栅极氧化物膜之间的界面处的粗糙度来抑制在MOSFET的栅极氧化膜中发生的漏电流。如果杂质浓度在源极区的表面部分变高，则通过干法氧化或CVD法形成栅极氧化膜。如果通过湿式氧化形成栅极氧化膜，则源极区域的表面部分处的杂质浓度被控制在低水平。

7. 发明授权

US08461632B2 SiC semiconductor device and method of manufacturing the same 有权
公开(公告)号：US08461632B2
公开(公告)日：2013-06-11
申请号：US12911304
申请日：2010-10-25
申请人： Noriaki Tsuchiya , Yoichiro Tarui
发明人： Noriaki Tsuchiya , Yoichiro Tarui
IPC分类号： H01L21/02
CPC分类号： H01L21/266 , H01L21/047 , H01L23/544 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/7811 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.

8. 发明申请

US20120132912A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120132912A1
公开(公告)日：2012-05-31
申请号：US13299882
申请日：2011-11-18
申请人： Eisuke SUEKAWA , Yasunori Oritsuki , Yoichiro Tarui
发明人： Eisuke SUEKAWA , Yasunori Oritsuki , Yoichiro Tarui
IPC分类号： H01L29/04 , H01L29/12
CPC分类号： H01L29/7811 , H01L29/1608 , H01L29/45 , H01L29/456 , H01L29/4941 , H01L29/78 , H01L29/7802 , H01L29/7804 , H01L29/7815 , H01L29/861
摘要： A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n−-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.
摘要翻译：半导体器件的MOSFET单元包括形成在n漂移层的上部的多晶硅栅极电极和n +源极区域。层间绝缘膜覆盖栅电极。 Al源电极在层间绝缘膜上延伸。 Al栅极焊盘连接到栅电极。防止铝扩散的阻挡金属层插入在源电极和层间绝缘膜之间以及栅极焊盘和栅电极之间。

9. 发明申请

US20100314629A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 失效
标题翻译：硅碳化硅半导体器件
公开(公告)号：US20100314629A1
公开(公告)日：2010-12-16
申请号：US12867061
申请日：2008-02-12
申请人： Yoichiro Tarui , Kenichi Ohtsuka , Naruhisa Miura , Yoshinori Matsuno , Masayuki Imaizumi
发明人： Yoichiro Tarui , Kenichi Ohtsuka , Naruhisa Miura , Yoshinori Matsuno , Masayuki Imaizumi
IPC分类号： H01L31/0312
CPC分类号： H01L29/66068 , H01L23/3171 , H01L23/3192 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/7811 , H01L29/8611 , H01L29/8613 , H01L29/872 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.
摘要翻译：为了获得在作为半导体元件驱动的单元部分的周边中提供用于电场弛豫的其终端部分中的高温操作中的耐受电压的稳定性和可靠性的确保的碳化硅半导体器件，端部设有具有高耐热性的无机保护膜，所述无机保护膜形成在作为形成在电池单元侧的第一区域的阱区的暴露表面上，以及具有高电绝缘能力的有机保护膜，在形成于与阱区的外侧表面形成并且与电池部分隔开的电场弛豫区域的表面上以及在碳化硅层的暴露表面上的电荷的一点影响。

10. 发明申请

US20090261348A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20090261348A1
公开(公告)日：2009-10-22
申请号：US12063875
申请日：2006-05-09
申请人： Yoichiro Tarui , Ken-ichi Ohtsuka , Masayuki Imaizumi
发明人： Yoichiro Tarui , Ken-ichi Ohtsuka , Masayuki Imaizumi
IPC分类号： H01L29/24 , H01L21/265 , H01L21/22
CPC分类号： H01L29/0615 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/7811 , H01L29/8611 , H01L29/94
摘要： In a semiconductor device using a SiC substrate, a Junction Termination Edge (JTE) layer is hardly affected by fixed charge so that a stable dielectric strength is obtained. A semiconductor device according to a first aspect of the present invention includes a SiC epi-layer having n type conductivity, an impurity region in a surface of the SiC epi-layer and having p type conductivity, and JTE layers adjacent to the impurity region, having p type conductivity, and having a lower impurity concentration than the impurity region. The JTE layers are spaced by a distance from an upper surface of the SiC epi-layer, and SiC regions having n type conductivity are present on the JTE layers.
摘要翻译：在使用SiC衬底的半导体器件中，结终端边缘（JTE）层几乎不受固定电荷的影响，从而获得稳定的介电强度。根据本发明的第一方面的半导体器件包括具有n型导电性的SiC外延层，在SiC外延层的表面中具有p型导电性的杂质区域和与杂质区域相邻的JTE层，具有p型导电性，并且具有比杂质区更低的杂质浓度。 JTE层与SiC外延层的上表面隔开一段距离，并且具有n型导电性的SiC区域存在于JTE层上。

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