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1. 发明授权

US07605081B2 Sub-lithographic feature patterning using self-aligned self-assembly polymers 有权
标题翻译：使用自对准自组装聚合物的亚光刻特征图案
公开(公告)号：US07605081B2
公开(公告)日：2009-10-20
申请号：US11424963
申请日：2006-06-19
申请人： Haining Yang , Wai-Kin Li
发明人： Haining Yang , Wai-Kin Li
IPC分类号： H01L21/44
CPC分类号： H01L21/31144 , G03F7/0002 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/76816
摘要： A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w
摘要翻译：提供了一种用于进行子光刻特征图案化的器件结构的方法。首先，通过在器件结构的上表面上的光刻和蚀刻来形成包含直径d的一个或多个掩模开口的光刻图案掩模层。接下来，将一层自组装嵌段共聚物施加在光刻图案化的掩模层上，然后退火以在每个掩模开口内形成直径为w的单个单元聚合物嵌段，条件是w

2. 发明申请

US20080132070A1 FULLY AND UNIFORMLY SILICIDED GATE STRUCTURE AND METHOD FOR FORMING SAME 失效
标题翻译：完全和均匀的硅胶结构及其形成方法
公开(公告)号：US20080132070A1
公开(公告)日：2008-06-05
申请号：US11566848
申请日：2006-12-05
申请人： Wai-Kin Li , Haining Yang
发明人： Wai-Kin Li , Haining Yang
IPC分类号： H01L21/44
CPC分类号： H01L29/42316 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/78 , Y10S977/892
摘要： Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.
摘要翻译：通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。退火步骤将多晶硅转化为硅化物。由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

3. 发明申请

US20080099845A1 SUB-LITHOGRAPHIC GATE LENGTH TRANSISTOR USING SELF-ASSEMBLING POLYMERS 有权
标题翻译：使用自组装聚合物的次平面栅长度晶体管
公开(公告)号：US20080099845A1
公开(公告)日：2008-05-01
申请号：US11552641
申请日：2006-10-25
申请人： Haining Yang , Wai-Kin Li
发明人： Haining Yang , Wai-Kin Li
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392 , H01L21/8238
CPC分类号： H01L21/28123 , B81C1/00031 , B81C2201/0149 , B82Y30/00 , G03F7/0002 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L29/66583 , H01L29/78
摘要： A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个晶体管的半导体结构，其中所述至少一个晶体管具有亚光刻沟道长度。还提供了使用可以使用预制的硬掩模图案放置在特定位置的自组装嵌段共聚物来形成这种半导体结构的方法。

4. 发明授权

US07863186B2 Fully and uniformly silicided gate structure and method for forming same 有权
标题翻译：完全均匀的硅化栅结构及其形成方法
公开(公告)号：US07863186B2
公开(公告)日：2011-01-04
申请号：US12334746
申请日：2008-12-15
申请人： Wai-Kin Li , Haining Yang
发明人： Wai-Kin Li , Haining Yang
IPC分类号： H01L21/44
CPC分类号： H01L29/42316 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/78 , Y10S977/892
摘要： Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.
摘要翻译：通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。退火步骤将多晶硅转化为硅化物。由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

5. 发明授权

US07592247B2 Sub-lithographic local interconnects, and methods for forming same 失效
标题翻译：亚光刻局部互连及其形成方法
公开(公告)号：US07592247B2
公开(公告)日：2009-09-22
申请号：US11538550
申请日：2006-10-04
申请人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
发明人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , B82Y10/00 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L23/485 , H01L27/11 , H01L27/1104
摘要： The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.
摘要翻译：本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接其间没有任何金属接触。可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

6. 发明申请

US20090200674A1 STRUCTURE AND METHOD OF FORMING TRANSITIONAL CONTACTS BETWEEN WIDE AND THIN BEOL WIRINGS 审中-公开
标题翻译：结构和方法在宽和小波纹之间形成过渡联系
公开(公告)号：US20090200674A1
公开(公告)日：2009-08-13
申请号：US12027448
申请日：2008-02-07
申请人： Haining Yang , Wai-Kin Li
发明人： Haining Yang , Wai-Kin Li
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76813 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric layer; etching an interconnect trench in the said second dielectric layer; etching a interconnect via using a photo resist mask to form a first portion of the transitional via; reacting the photo resist to expand the photo resist at least in the lateral direction; etching the said dielectric layer using the reacted photo resist to form the second portion of the transitional via; and filling the said interconnect trench and the said interconnect via with metal.
摘要翻译：描述了形成用于连接线路的两个后端（BEOL）金属布线层的导电通孔的结构和方法。该方法包括在第一介电层中形成具有第一尺寸宽度的第一互连结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻所述第二介电层中的互连沟槽; 通过使用光刻胶掩模蚀刻互连以形成过渡通孔的第一部分; 使光致抗蚀剂反应至少在横向上扩展光致抗蚀剂; 使用反应的光致抗蚀剂蚀刻所述介电层以形成过渡通孔的第二部分; 以及用金属填充所述互连沟槽和所述互连通孔。

7. 发明申请

US20080164558A1 METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION STRUCTURES USING DIBLOCK COPOLYMER PATTERNING 失效
标题翻译：使用二嵌段共聚物图案制作浅层分离结构的方法
公开(公告)号：US20080164558A1
公开(公告)日：2008-07-10
申请号：US11621124
申请日：2007-01-09
申请人： Haining Yang , Wai-Kin Li
发明人： Haining Yang , Wai-Kin Li
IPC分类号： H01L23/00 , H01L21/762
CPC分类号： H01L21/76283 , H01L21/3086
摘要： A method of isolating semiconductor devices formed on a semiconductor substrate having a silicon on insulator (SOI) layer is provided. The method includes forming at least one shallow trench area on a pad nitride layer deposited on a surface of the SOI layer, wherein the at least one shallow trench area includes an opening for exposing a portion of the SOI layer; applying diblock copolymer material over the pad nitride layer and the at least one shallow trench area; annealing the applied copolymer material to form self-organized patterns; and partially etching the shallow trench area using the diblock copolymer material as an etch mask. A semiconductor structures is also described having an isolation structure formed on a SOI layer of a semiconductor substrate the isolation structure having an oxidized substrate region; and a void region formed on the oxidized substrate region.
摘要翻译：提供了一种隔离形成在具有绝缘体上硅（SOI）层的半导体衬底上的半导体器件的方法。该方法包括在沉积在SOI层的表面上的衬垫氮化物层上形成至少一个浅沟槽区，其中至少一个浅沟槽区包括用于暴露SOI层的一部分的开口; 在所述衬垫氮化物层和所述至少一个浅沟槽区域上施加二嵌段共聚物材料; 退火所应用的共聚物材料以形成自组织图案; 并使用二嵌段共聚物材料作为蚀刻掩模部分蚀刻浅沟槽区域。还描述了半导体结构，其具有形成在半导体衬底的SOI层上的隔离结构，该隔离结构具有氧化的衬底区域; 以及形成在氧化的基板区域上的空隙区域。

8. 发明申请

US20080083991A1 SUB-LITHOGRAPHIC LOCAL INTERCONNECTS, AND METHODS FOR FORMING SAME 失效
标题翻译：次平面局部互连及其形成方法
公开(公告)号：US20080083991A1
公开(公告)日：2008-04-10
申请号：US11538550
申请日：2006-10-04
申请人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
发明人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
IPC分类号： H01L23/52
CPC分类号： H01L21/76895 , B82Y10/00 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L23/485 , H01L27/11 , H01L27/1104
摘要： The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.
摘要翻译：本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接其间没有任何金属接触。可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

9. 发明授权

US08476674B2 Gate conductor with a diffusion barrier 有权
标题翻译：具有扩散阻挡层的栅极导体
公开(公告)号：US08476674B2
公开(公告)日：2013-07-02
申请号：US13010009
申请日：2011-01-20
申请人： Wai-Kin Li , Haining Yang
发明人： Wai-Kin Li , Haining Yang
IPC分类号： H01L29/66 , H01L27/118
CPC分类号： H01L21/76841 , H01L21/823842 , H01L21/823871 , H01L22/12 , H01L23/58 , H01L29/42376 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.
摘要翻译：提供了具有在N型器件和P型器件之间的势垒区域的栅极导体结构，其中所述势垒区域最小化或消除了所述阻挡区域上的掺杂剂物质的交叉扩散。阻挡区域包括栅极导体结构中的至少一个亚光刻间隙。通过使用自组装共聚物在栅极导体结构上形成亚光刻图案掩模来形成亚光刻间隙。根据一个实施例，至少一个亚光刻间隙是穿过栅极导体结构的宽度的狭缝或线。亚光刻间隙足够深以使注入的掺杂剂从栅极导体的上部最小化或防止交叉扩散。根据另一个实施例，亚光刻间隙具有足够的密度，使得在激活退火期间掺杂剂的交叉扩散减少或消除，使得Vt的变化最小化。

10. 发明授权

US07790540B2 Structure and method to use low k stress liner to reduce parasitic capacitance 失效
标题翻译：使用低k应力衬垫降低寄生电容的结构和方法
公开(公告)号：US07790540B2
公开(公告)日：2010-09-07
申请号：US11467186
申请日：2006-08-25
申请人： Haining Yang , Wai-Kin Li
发明人： Haining Yang , Wai-Kin Li
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/092 , H01L29/7843
摘要： A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.
摘要翻译：提供了一种代替CMOS器件中常规应力衬垫的低k应力衬垫。在一个实施例中，提供压缩的低k应力衬垫，其可以改善pFET器件中的空穴迁移率。这种压缩低k材料的紫外线暴露导致低k应力衬垫的极性从压缩变为拉伸。使用这种拉伸的低k应力衬垫提高nFET器件中的电子迁移率。

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