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1. 发明授权

US07592247B2 Sub-lithographic local interconnects, and methods for forming same 失效
标题翻译：亚光刻局部互连及其形成方法
公开(公告)号：US07592247B2
公开(公告)日：2009-09-22
申请号：US11538550
申请日：2006-10-04
申请人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
发明人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , B82Y10/00 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L23/485 , H01L27/11 , H01L27/1104
摘要： The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.
摘要翻译：本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接其间没有任何金属接触。可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

2. 发明申请

US20080083991A1 SUB-LITHOGRAPHIC LOCAL INTERCONNECTS, AND METHODS FOR FORMING SAME 失效
标题翻译：次平面局部互连及其形成方法
公开(公告)号：US20080083991A1
公开(公告)日：2008-04-10
申请号：US11538550
申请日：2006-10-04
申请人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
发明人： Haining Yang , Jack A. Mandelman , Wai-Kin Li
IPC分类号： H01L23/52
CPC分类号： H01L21/76895 , B82Y10/00 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L23/485 , H01L27/11 , H01L27/1104
摘要： The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.
摘要翻译：本发明涉及一种具有第一和第二有源器件区域的半导体器件，该半导体器件区域位于半导体衬底中并且通过它们之间的隔离区彼此隔离，而半导体器件包含宽度范围的第一子光刻互连结构从约20nm至约40nm，用于将第一有源器件区域与第二有源器件区域连接。半导体器件优选地包含位于半导体衬底中的至少一个静态随机存取存储器（SRAM）单元，并且第一子光刻互连结构直接将SRAM单元的下拉晶体管与其上拉晶体管交叉连接其间没有任何金属接触。可以通过掩模层的光刻图案容易地形成第一亚光刻互连结构，然后使用自组装嵌段共聚物或电介质侧壁间隔物形成亚光刻特征。

3. 发明授权

US06642566B1 Asymmetric inside spacer for vertical transistor 失效
标题翻译：垂直晶体管的不对称内隔板
公开(公告)号：US06642566B1
公开(公告)日：2003-11-04
申请号：US10195601
申请日：2002-06-28
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Haining Yang
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Haining Yang
IPC分类号： H01L2708
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10888 , H01L27/10891
摘要： A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.
摘要翻译：具有使用垂直晶体管的DRAM单元的DRAM阵列通过在字线和晶体管之间的连接中使用不对称结构来增加电可靠性并降低位线电容，从而允许在字线和晶体管电极之间使用更宽的连接并且使用该字线作为蚀刻停止以在图形化字线期间保护晶体管栅极。

4. 发明授权

US08008713B2 Vertical SOI trench SONOS cell 有权
标题翻译：垂直SOI沟槽SONOS单元
公开(公告)号：US08008713B2
公开(公告)日：2011-08-30
申请号：US12410935
申请日：2009-03-25
申请人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
发明人： David M. Dobuzinsky , Herbert L. Ho , Jack A. Mandelman , Yoichi Otani
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , H01L21/26586 , H01L27/115 , H01L27/11568 , H01L29/7926
摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

5. 发明授权

US07804148B2 Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer 失效
标题翻译：光热掩模包括对准的热耗散层，反射层和透明覆盖层
公开(公告)号：US07804148B2
公开(公告)日：2010-09-28
申请号：US11355799
申请日：2006-02-16
申请人： Louis L. Hsu , Jack A. Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
发明人： Louis L. Hsu , Jack A. Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
IPC分类号： H01L23/58 , H01L31/058 , H01L31/02 , H01L31/0232 , H01L31/024 , H01L21/033 , H01L21/00
CPC分类号： H01L21/268 , H01L21/84 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.
摘要翻译：光热退火掩模层叠层包括位于衬底上的散热层。反射层位于热耗散层上。可以具有约10至约100埃厚度的透明覆盖层位于反射层上。光热退火掩模层可以用作场效应器件中的栅电极。

6. 发明申请

US20100230781A1 TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT 有权
标题翻译：用于可编程集成电路的抗融合结构
公开(公告)号：US20100230781A1
公开(公告)日：2010-09-16
申请号：US12537473
申请日：2009-08-07
申请人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.
摘要翻译：沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层沟槽的侧壁。电介质层设置在导电插塞和掺杂区域之间。电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

7. 发明授权

US07790530B2 Dual port gain cell with side and top gated read transistor 失效
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07790530B2
公开(公告)日：2010-09-07
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

8. 发明授权

US07656005B2 Electrically programmable π-shaped fuse structures and methods of fabrication thereof 失效
标题翻译：电气可编程的pi形熔丝结构及其制造方法
公开(公告)号：US07656005B2
公开(公告)日：2010-02-02
申请号：US11768254
申请日：2007-06-26
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译：提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

9. 发明授权

US07642588B2 Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same 有权
标题翻译：具有平面FET的存储单元和仅在沟槽的上部区域中的区域的垂直FET，以及制造和使用它们的方法
公开(公告)号：US07642588B2
公开(公告)日：2010-01-05
申请号：US11259296
申请日：2005-10-26
申请人： Kangguo Cheng , Jack A. Mandelman
发明人： Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , G11C11/403 , G11C11/405 , H01L27/0207 , H01L27/10864 , H01L27/10894 , H01L29/045
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell of a substrate that includes (1) a PFET with an orientation approximately planar to a surface of the substrate; and (2) an NFET coupled to the approximately planar PFET. An orientation of the NFET in the substrate is approximately perpendicular to the orientation of the PFET. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种第一装置。第一装置是基板的存储单元，其包括（1）具有与基板的表面近似平面的取向的PFET; 和（2）耦合到大致平面PFET的NFET。衬底中NFET的取向近似垂直于PFET的取向。提供了许多其他方面。

10. 发明申请

US20090244954A1 STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS 有权
标题翻译：改善存储容量对单一事件的可靠性的结构和方法
公开(公告)号：US20090244954A1
公开(公告)日：2009-10-01
申请号：US12055509
申请日：2008-03-26
申请人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Ethan H. Cannon , Toshiharu Furukawa , David Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： G11C11/40 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , G11C11/4125 , H01L27/0921 , H01L27/1104 , H01L29/66181 , H03K3/0375
摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).
摘要翻译：数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

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