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1. 发明申请

US20070054196A1 Fabrication method of extreme ultraviolet radiation mask mirror using atomic force microscope lithography 失效
标题翻译：使用原子力显微镜光刻的极紫外辐射掩模镜的制造方法
公开(公告)号：US20070054196A1
公开(公告)日：2007-03-08
申请号：US10578683
申请日：2004-06-08
申请人： Hai Lee , Sun Lee , Jin Ahn , Suk Bae
发明人： Hai Lee , Sun Lee , Jin Ahn , Suk Bae
IPC分类号： G03F1/00
CPC分类号： G03F1/24 , B82Y10/00 , B82Y30/00 , B82Y40/00 , G03F7/2049
摘要： The present invention relates to a method for manufacturing a reflective multi-layered thin film mirror for an extreme ultraviolet radiation (EUV) exposure process that is one of the next generation exposure process masks using an atomic force microscope (AFM). This reflective multi-layered thin film mirror for extreme ultraviolet radiation (EUV) exposure process allows metal oxide structures with fixed height and width to be obtained using anodic oxidization phenomenon between the cantilever tip of a atomic force microscope and an absorber material during the patterning of an absorber layer on a multi-layered thin film of a substrate, followed by forming the ultra-fine line width absorber patterns via etching of the metal oxide structure. Use of the manufacturing process of this invention is advantageous in manufacturing of extreme ultraviolet radiation exposure mask mirrors with high resolution and in manufacturing of reflective multi-layered thin film mirrors with minute absorber pattern sizes (less than 20 nm line width) compared to traditional manufacturing methods.
摘要翻译：本发明涉及一种制造用于使用原子力显微镜（AFM）的下一代曝光处理掩模之一的用于极紫外辐射（EUV）曝光工艺的反射型多层薄膜反射镜的方法。这种用于极紫外辐射（EUV）曝光工艺的反光多层薄膜反射镜允许使用原子力显微镜的悬臂尖端与吸收材料之间的阳极氧化现象在图案化期间获得具有固定高度和宽度的金属氧化物结构在基板的多层薄膜上形成吸收层，然后通过金属氧化物结构的蚀刻形成超细线宽度的吸收体图案。使用本发明的制造方法在制造具有高分辨率的极紫外辐射曝光掩模反射镜和制造具有小的吸收体图案尺寸（小于20nm线宽）的反射多层薄膜反射镜相比传统制造方面是有利的方法。

2. 发明申请

US20050001304A1 Chip scale package and method of fabricating the same 失效
标题翻译：芯片尺寸封装及其制造方法
公开(公告)号：US20050001304A1
公开(公告)日：2005-01-06
申请号：US10879157
申请日：2004-06-30
申请人： Joon Yoon , Yong Choi , Suk Bae
发明人： Joon Yoon , Yong Choi , Suk Bae
IPC分类号： H01L23/12 , H01L21/301 , H01L21/304 , H01L21/60 , H01L23/04 , H01L23/31 , H01L23/485 , H01L33/38 , H01L33/62 , H05K3/34 , H01L23/495 , H01L21/44 , H01L23/02
CPC分类号： H01L24/10 , H01L23/3114 , H01L24/13 , H01L24/48 , H01L33/38 , H01L33/62 , H01L2224/05571 , H01L2224/05573 , H01L2224/13 , H01L2224/13099 , H01L2224/48091 , H01L2924/00014 , H01L2924/00015 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H05K3/3442 , H05K2201/09381 , H05K2201/10166 , Y02P70/613 , H01L2924/00 , H01L2224/45099 , H01L2224/85399 , H01L2224/05599 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises an insulating layer formed on the upper surface of a chip provided with a plurality of terminals on its one surface, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surfaces formed on each of the upper surfaces of a plurality of the conductive layers. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.
摘要翻译：公开了一种芯片级封装和一种制造芯片级封装的方法。芯片级封装包括在其一个表面上设置有多个端子的芯片的上表面上形成的绝缘层，形成在绝缘层上并以指定距离彼此隔开的多个导电层，连接到多个端子中的每一个，以及形成在多个导电层的每个上表面上的多个电极表面。芯片尺寸封装在整个封装尺寸上小型化。此外，制造芯片级封装的方法不需要引线键合步骤或通孔形成步骤，从而简化了芯片级封装的制造工艺，并提高了芯片级封装的可靠性。

3. 发明申请

US20050087848A1 Chip scale package and method of fabricating the same 失效
标题翻译：芯片尺寸封装及其制造方法
公开(公告)号：US20050087848A1
公开(公告)日：2005-04-28
申请号：US10988523
申请日：2004-11-16
申请人： Joon Yoon , Yong Choi , Suk Bae
发明人： Joon Yoon , Yong Choi , Suk Bae
IPC分类号： H01L23/12 , H01L21/60 , H01L21/78 , H01L23/31 , H01L23/48 , H01L23/485 , H05K3/34 , H05K5/00 , H01L21/48 , H01L29/40
CPC分类号： H05K5/0091 , H01L21/78 , H01L23/3114 , H01L24/05 , H01L24/48 , H01L24/97 , H01L2224/04042 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4848 , H01L2224/73265 , H01L2224/85051 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15787 , H01L2924/181 , H05K3/3442 , H05K2201/09381 , H05K2201/10636 , Y02P70/611 , Y02P70/613 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： Disclosed are a chip scale package and a method of fabricating the chip scale package. The chip scale package comprises conductive layers with a designated depth formed on an upper and a lower surfaces of a chip, and electrode surfaces formed on the same side surfaces of the conductive layers, which are connected to corresponding connection pads of a printed circuit board. The chip scale package is miniaturized in the whole package size. Further, the method of fabricating the chip scale package does not require a wire-bonding step or a via hole forming step, thereby simplifying the fabrication process of the chip scale package and improving the reliability of the chip scale package.
摘要翻译：公开了一种芯片级封装和一种制造芯片级封装的方法。芯片级封装包括形成在芯片的上表面和下表面上的指定深度的导电层，以及形成在导电层的相同侧表面上并连接到印刷电路板的相应连接焊盘的电极表面。芯片尺寸封装在整个封装尺寸上小型化。此外，制造芯片级封装的方法不需要引线键合步骤或通孔形成步骤，从而简化了芯片级封装的制造工艺，并提高了芯片级封装的可靠性。

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