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    • 1. 发明申请
    • METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH METAL LINE
    • 用金属线制造半导体器件的方法
    • US20100062598A1
    • 2010-03-11
    • US12618523
    • 2009-11-13
    • Hae-Jung LEESang-Hoon ChoSuk-Ki Kim
    • Hae-Jung LEESang-Hoon ChoSuk-Ki Kim
    • H01L21/768
    • H01L21/76877H01L21/32115H01L21/32136H01L21/76843H01L21/76849
    • A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
    • 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分,所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层,所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。
    • 2. 发明授权
    • Method for fabricating semiconductor device with metal line
    • 用金属线制造半导体器件的方法
    • US07648909B2
    • 2010-01-19
    • US11321533
    • 2005-12-30
    • Hae-Jung LeeSang-Hoon ChoSuk-Ki Kim
    • Hae-Jung LeeSang-Hoon ChoSuk-Ki Kim
    • H01L21/4763
    • H01L21/76877H01L21/32115H01L21/32136H01L21/76843H01L21/76849
    • A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
    • 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分,所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层,所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。
    • 3. 发明申请
    • Method for fabricating semiconductor device with metal line
    • 用金属线制造半导体器件的方法
    • US20060246708A1
    • 2006-11-02
    • US11321533
    • 2005-12-30
    • Hae-Jung LeeSang-Hoon ChoSuk-Ki Kim
    • Hae-Jung LeeSang-Hoon ChoSuk-Ki Kim
    • H01L21/4763H01L21/44
    • H01L21/76877H01L21/32115H01L21/32136H01L21/76843H01L21/76849
    • A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
    • 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分,所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层,所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。
    • 4. 发明授权
    • Method for fabricating semiconductor device with metal line
    • 用金属线制造半导体器件的方法
    • US08030205B2
    • 2011-10-04
    • US12618523
    • 2009-11-13
    • Hae-Jung LeeSang-Hoon ChoSuk-Ki Kim
    • Hae-Jung LeeSang-Hoon ChoSuk-Ki Kim
    • H01L21/4763
    • H01L21/76877H01L21/32115H01L21/32136H01L21/76843H01L21/76849
    • A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
    • 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分,所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层,所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。
    • 7. 发明授权
    • Semiconductor device and method of fabricating the same
    • 半导体装置及其制造方法
    • US08294207B2
    • 2012-10-23
    • US13168301
    • 2011-06-24
    • Sang-Hoon ChoYun-Seok ChoMyung-Ok KimSang-Hoon ParkYoung-Kyun Jung
    • Sang-Hoon ChoYun-Seok ChoMyung-Ok KimSang-Hoon ParkYoung-Kyun Jung
    • H01L29/78
    • H01L21/823487H01L29/66666
    • In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
    • 在一种在包括多个柱状图案的基板上制造半导体器件的方法中,相邻柱状图案之间的杂质区域,每个柱状图案上的栅极电极,覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层 在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层,形成覆盖栅电极的牺牲层,在每个柱状图案的侧壁上形成第二覆盖层 ,去除牺牲层,并且形成连接相邻柱状图案的栅电极的字线。 在所制造的器件中,第一覆盖层将杂质区域与字线隔离,并且第二封盖区域防止相应柱状图案的侧壁暴露。
    • 8. 发明申请
    • METHOD FOR PATTERNING SEMICONDUCTOR DEVICE HAVING MAGNETIC TUNNELING JUNCTION STRUCTURE
    • 用于绘制具有磁性隧道结结构的半导体器件的方法
    • US20100055804A1
    • 2010-03-04
    • US12492697
    • 2009-06-26
    • Sang-Hoon Cho
    • Sang-Hoon Cho
    • H01L21/306
    • H01L43/12G11C11/161
    • A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.
    • 一种用于图案化半导体器件的方法包括在衬底上形成下电极导电层,在衬底上形成包括下电极导电层,第一铁磁层,绝缘层和第二铁磁层的堆叠结构,形成上电极 导电层,用作叠层结构上的第一硬掩模,在上电极导电层上形成第二硬掩模层,选择性地蚀刻第二硬掩模层以形成第二硬掩模图案,使用第二硬掩模层蚀刻第二硬掩模图案 硬掩模图案作为蚀刻阻挡层以形成上电极,并且至少使用上电极作为蚀刻阻挡层来蚀刻包括下电极导电层,第一铁磁层,绝缘层和第二铁磁层的堆叠结构。
    • 9. 发明授权
    • Method of fabricating a semiconductor device with a channel formed in a vertical direction
    • 制造具有在垂直方向上形成的通道的半导体器件的方法
    • US07989292B2
    • 2011-08-02
    • US12334324
    • 2008-12-12
    • Sang-Hoon ChoYun-Seok ChoMyung-Ok KimSang-Hoon ParkYoung-Kyun Jung
    • Sang-Hoon ChoYun-Seok ChoMyung-Ok KimSang-Hoon ParkYoung-Kyun Jung
    • H01L21/336
    • H01L21/823487H01L29/66666
    • In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
    • 在一种在包括多个柱状图案的基板上制造半导体器件的方法中,相邻柱状图案之间的杂质区域,每个柱状图案上的栅极电极,覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层 在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层,形成覆盖栅电极的牺牲层,在每个柱状图案的侧壁上形成第二覆盖层 ,去除牺牲层,并且形成连接相邻柱状图案的栅电极的字线。 在所制造的器件中,第一覆盖层将杂质区域与字线隔离,并且第二封盖区域防止相应柱状图案的侧壁暴露。