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1. 发明申请

US20100062598A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH METAL LINE 失效
标题翻译：用金属线制造半导体器件的方法
公开(公告)号：US20100062598A1
公开(公告)日：2010-03-11
申请号：US12618523
申请日：2009-11-13
申请人： Hae-Jung LEE , Sang-Hoon Cho , Suk-Ki Kim
发明人： Hae-Jung LEE , Sang-Hoon Cho , Suk-Ki Kim
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/32115 , H01L21/32136 , H01L21/76843 , H01L21/76849
摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

2. 发明授权

US07648909B2 Method for fabricating semiconductor device with metal line 失效
标题翻译：用金属线制造半导体器件的方法
公开(公告)号：US07648909B2
公开(公告)日：2010-01-19
申请号：US11321533
申请日：2005-12-30
申请人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
发明人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/32115 , H01L21/32136 , H01L21/76843 , H01L21/76849
摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

3. 发明申请

US20060246708A1 Method for fabricating semiconductor device with metal line 失效
标题翻译：用金属线制造半导体器件的方法
公开(公告)号：US20060246708A1
公开(公告)日：2006-11-02
申请号：US11321533
申请日：2005-12-30
申请人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
发明人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/32115 , H01L21/32136 , H01L21/76843 , H01L21/76849
摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

4. 发明授权

US08030205B2 Method for fabricating semiconductor device with metal line 失效
标题翻译：用金属线制造半导体器件的方法
公开(公告)号：US08030205B2
公开(公告)日：2011-10-04
申请号：US12618523
申请日：2009-11-13
申请人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
发明人： Hae-Jung Lee , Sang-Hoon Cho , Suk-Ki Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/32115 , H01L21/32136 , H01L21/76843 , H01L21/76849
摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

5. 发明授权

US07858476B2 Method for fabricating semiconductor device with recess gate 失效
标题翻译：用于制造具有凹槽的半导体器件的方法
公开(公告)号：US07858476B2
公开(公告)日：2010-12-28
申请号：US11928056
申请日：2007-10-30
申请人： Yong-Tae Cho , Suk-Ki Kim , Sang-Hoon Cho
发明人： Yong-Tae Cho , Suk-Ki Kim , Sang-Hoon Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/3065 , H01L21/3083 , H01L21/3086
摘要： A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.
摘要翻译：一种用于制造半导体器件的方法包括：在衬底上形成硬掩模图案，在衬底中形成第一凹槽，并使用硬掩模图案作为蚀刻阻挡层，在第一凹槽的侧壁上形成钝化层，并形成第二凹槽使用钝化层蚀刻第一凹部的底部作为蚀刻阻挡层，其中第二凹部的宽度大于第一凹部的宽度。

6. 发明申请

US20070004194A1 Method for fabricating semiconductor device with deep opening 审中-公开
标题翻译：半导体器件深度开放的方法
公开(公告)号：US20070004194A1
公开(公告)日：2007-01-04
申请号：US11321593
申请日：2005-12-30
申请人： Yong-Tae Cho , Hae-Jung Lee , Sang-Hoon Cho
发明人： Yong-Tae Cho , Hae-Jung Lee , Sang-Hoon Cho
IPC分类号： H01L21/4763
CPC分类号： H01L27/10852 , H01L21/76802 , H01L21/76844
摘要： A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form first openings; enlarging areas of the first openings; forming anti-bowing spacers on sidewalls of the enlarged first openings; and etching portions of the insulation layer remaining beneath the enlarged first openings to form second openings.
摘要翻译：提供一种制造具有深开口的半导体器件的方法。该方法包括：在基板上形成绝缘层; 选择性地蚀刻绝缘层以形成第一开口; 扩大开放区域; 在扩大的第一开口的侧壁上形成抗弓形间隔物; 以及蚀刻保留在扩大的第一开口下方的部分以形成第二开口。

7. 发明授权

US08294207B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08294207B2
公开(公告)日：2012-10-23
申请号：US13168301
申请日：2011-06-24
申请人： Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
发明人： Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
IPC分类号： H01L29/78
CPC分类号： H01L21/823487 , H01L29/66666
摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
摘要翻译：在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。

8. 发明申请

US20100055804A1 METHOD FOR PATTERNING SEMICONDUCTOR DEVICE HAVING MAGNETIC TUNNELING JUNCTION STRUCTURE 失效
标题翻译：用于绘制具有磁性隧道结结构的半导体器件的方法
公开(公告)号：US20100055804A1
公开(公告)日：2010-03-04
申请号：US12492697
申请日：2009-06-26
申请人： Sang-Hoon Cho
发明人： Sang-Hoon Cho
IPC分类号： H01L21/306
CPC分类号： H01L43/12 , G11C11/161
摘要： A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.
摘要翻译：一种用于图案化半导体器件的方法包括在衬底上形成下电极导电层，在衬底上形成包括下电极导电层，第一铁磁层，绝缘层和第二铁磁层的堆叠结构，形成上电极导电层，用作叠层结构上的第一硬掩模，在上电极导电层上形成第二硬掩模层，选择性地蚀刻第二硬掩模层以形成第二硬掩模图案，使用第二硬掩模层蚀刻第二硬掩模图案硬掩模图案作为蚀刻阻挡层以形成上电极，并且至少使用上电极作为蚀刻阻挡层来蚀刻包括下电极导电层，第一铁磁层，绝缘层和第二铁磁层的堆叠结构。

9. 发明授权

US07989292B2 Method of fabricating a semiconductor device with a channel formed in a vertical direction 有权
标题翻译：制造具有在垂直方向上形成的通道的半导体器件的方法
公开(公告)号：US07989292B2
公开(公告)日：2011-08-02
申请号：US12334324
申请日：2008-12-12
申请人： Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
发明人： Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
IPC分类号： H01L21/336
CPC分类号： H01L21/823487 , H01L29/66666
摘要： In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
摘要翻译：在一种在包括多个柱状图案的基板上制造半导体器件的方法中，相邻柱状图案之间的杂质区域，每个柱状图案上的栅极电极，覆盖栅电极的第一覆盖层和覆盖该栅极电极的分离层在相邻柱状图案的栅电极之间的第一覆盖层除去除了与分离层接触的部分之外的第一覆盖层，形成覆盖栅电极的牺牲层，在每个柱状图案的侧壁上形成第二覆盖层，去除牺牲层，并且形成连接相邻柱状图案的栅电极的字线。在所制造的器件中，第一覆盖层将杂质区域与字线隔离，并且第二封盖区域防止相应柱状图案的侧壁暴露。

10. 发明授权

US07790552B2 Method for fabricating semiconductor device with bulb-shaped recess gate 失效
标题翻译：制造具有灯泡形凹槽的半导体器件的方法
公开(公告)号：US07790552B2
公开(公告)日：2010-09-07
申请号：US11803059
申请日：2007-05-11
申请人： Sang-Hoon Cho
发明人： Sang-Hoon Cho
IPC分类号： H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/66621 , H01L29/78
摘要： A method for fabricating a semiconductor device includes forming a plurality of bulb-shaped recesses in a substrate, forming a gate insulation layer over the substrate including the bulb-shaped recesses, forming a patterned first conductive layer over sidewalls of a bulb pattern of the corresponding bulb-shaped recesses, and forming a patterned second conductive layer over the gate insulation layer while filling the bulb-shaped recesses.
摘要翻译：一种制造半导体器件的方法包括在衬底中形成多个灯泡形凹槽，在包括灯泡形凹槽的衬底之上形成栅极绝缘层，在对应的灯泡图案的侧壁上形成图案化的第一导电层并且在填充灯泡状凹部的同时在栅绝缘层上形成图案化的第二导电层。

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