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1. 发明申请

US20140198576A1 PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES 审中-公开
标题翻译：用于减少堆叠存储器结构中的程序干扰的编程技术
公开(公告)号：US20140198576A1
公开(公告)日：2014-07-17
申请号：US13827475
申请日：2013-03-14
申请人： Shuo-Nan Hung , HANG-TING LUE , TI-WEN CHEN , SHIH-LIN HUANG , KUO-PIN CHANG , CHIH-CHANG HSIEH , CHUN-HSIUNG HUNG
发明人： Shuo-Nan Hung , HANG-TING LUE , TI-WEN CHEN , SHIH-LIN HUANG , KUO-PIN CHANG , CHIH-CHANG HSIEH , CHUN-HSIUNG HUNG
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2211/5621 , G11C2216/14 , H01L27/11551 , H01L27/11578
摘要： A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set.
摘要翻译：描述用于对具有多层存储器单元的堆叠存储器结构进行编程的编程偏置技术。该技术包括响应于程序指令的控制器电路，以在特定多位地址的单元堆栈中的目标单元格中编程数据。电路被配置为使用单元格堆栈中的单元格分配给多个单元组，并且迭代地执行依次选择多个集合中的每一个的设置程序操作。每个迭代包括对多个组中的其他单元中的所有单元施加抑制电压。此外，每组层包括一个或两个子集，并且存在至少两个层，其中一组将每个子集分隔开。

2. 发明申请

US20120281478A1 THERMALLY ASSISTED FLASH MEMORY WITH DIODE STRAPPING 有权
标题翻译：具有二极管缠绕的热辅助闪存
公开(公告)号：US20120281478A1
公开(公告)日：2012-11-08
申请号：US13458970
申请日：2012-04-27
申请人： HANG-TING LUE , Chun-Hsiung Hung
发明人： HANG-TING LUE , Chun-Hsiung Hung
IPC分类号： G11C16/04 , H01L21/8239
CPC分类号： G11C16/08 , G11C5/025 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/3495 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/1021 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L29/42324 , H01L29/42328 , H01L29/4234 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.
摘要翻译：存储器包括包括行和列的存储单元阵列。存储器包括耦合到字线的电路，在施加与第一偏置电压不同的第二偏置电压的同时，将第一偏置电压施加到阵列中的字线或字线上的第一组间隔开的位置，在字线或字线上的一组间隔开的位置，第一组间隔开的位置中的位置在第二组间隔开的位置中的位置之间交错，从而在第一和第二位置之间的位置之间感应出电流导致字线或字线加热的位置集合。

3. 发明申请

US20070290273A1 OPERATING METHOD OF NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US20070290273A1
公开(公告)日：2007-12-20
申请号：US11554455
申请日：2006-10-30
申请人： HANG-TING LUE , ERH-KUN LAI , SZU-YU WANG
发明人： HANG-TING LUE , ERH-KUN LAI , SZU-YU WANG
IPC分类号： H01L29/76
CPC分类号： H01L29/42324 , G11C16/0466 , G11C16/0483 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/513
摘要： An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the channel region, a charge storage layer disposed on the insulating layer, a multi-layer tunneling dielectric structure on the charge storage layer, and a gate disposed on the multi-layer tunneling dielectric structure. A negative bias is supplied to the gate to inject electrons into the charge storage layer through the multi-layer tunneling dielectric structure by −FN tunneling so that the threshold voltage of the device is increased. A positive bias is supplied to the gate to inject holes into the charge storage layer through the multi-layer tunneling dielectric structure by +FN tunneling so that the threshold voltage of the device is decreased.
摘要翻译：提供了一种非易失性存储器件的操作方法。该器件包括具有半导体衬底，堆叠层以及设置在衬底的表面下方并由沟道区分隔开的源极和漏极区的存储单元。堆叠层包括设置在沟道区上的绝缘层，设置在绝缘层上的电荷存储层，电荷存储层上的多层隧道电介质结构，以及设置在多层隧道电介质结构上的栅极。向栅极提供负偏压，通过多沟道介质结构通过-FN隧穿将电子注入电荷存储层，从而增加器件的阈值电压。向栅极提供正偏压，以通过+ FN隧穿通过多层隧道电介质结构将空穴注入电荷存储层，使得器件的阈值电压降低。

4. 发明申请

US20120074486A1 MULTI-GATE BANDGAP ENGINEERED MEMORY 有权
标题翻译：多门带工程存储器
公开(公告)号：US20120074486A1
公开(公告)日：2012-03-29
申请号：US13310546
申请日：2011-12-02
申请人： HANG-TING LUE , Szu-Yu Wang
发明人： HANG-TING LUE , Szu-Yu Wang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , G11C16/0483 , G11C16/0491 , H01L21/265 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.
摘要翻译：存储单元包括：半导体衬底，其具有设置在衬底的表面下方并由沟道区分隔开的源极区和漏极区; 隧道介电结构，其设置在所述沟道区上方，所述隧道介电结构包括至少一层具有空穴隧道势垒高度的层; 设置在隧道介电结构上方的电荷存储层; 设置在电荷存储层上方的绝缘层; 并且设置在绝缘层上方的栅极电极与阵列和操作方法一起被描述。

5. 发明申请

US20100176438A1 DEPLETION-MODE CHARGE-TRAPPING FLASH DEVICE 有权
标题翻译：分离模式充电捕捉闪存器件
公开(公告)号：US20100176438A1
公开(公告)日：2010-07-15
申请号：US12553758
申请日：2009-09-03
申请人： HANG-TING LUE , Yi-Hsuan Hsiao
发明人： HANG-TING LUE , Yi-Hsuan Hsiao
IPC分类号： H01L27/115
CPC分类号： H01L29/792 , G11C16/0483 , H01L27/11568 , H01L29/513
摘要： A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.
摘要翻译：存储器件在衬底上包括多个半导体线，例如体结翅片。这些线包括掺杂用于耗尽模式操作的掩埋沟道区。存储结构位于多条线上，包括鳍状物的沟道区上的隧道绝缘层，隧道绝缘层上的电荷存储层，以及电荷存储层上的阻挡绝缘层。多个字线覆盖在存储结构上并与半导体线的沟道区交叉，由此存储单元位于字线和半导体线的交叉点。

6. 发明申请

US20130343130A1 NAND FLASH BIASING OPERATION 有权
标题翻译： NAND闪存偏移操作
公开(公告)号：US20130343130A1
公开(公告)日：2013-12-26
申请号：US13710992
申请日：2012-12-11
申请人： TI-WEN CHEN , HANG-TING LUE , SHUO-NAN HUNG , SHIH-LIN HUANG , CHIH-CHANG HSIEH , KUO-PIN CHANG
发明人： TI-WEN CHEN , HANG-TING LUE , SHUO-NAN HUNG , SHIH-LIN HUANG , CHIH-CHANG HSIEH , KUO-PIN CHANG
IPC分类号： G11C16/06
CPC分类号： G11C16/26 , G11C5/146 , G11C11/5642 , G11C16/0483 , G11C16/06 , G11C16/24 , H01L27/11524 , H01L27/1157
摘要： A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.
摘要翻译：电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线在操作期间转变为各种电压。

7. 发明申请

US20100155821A1 STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：堆叠的非易失性存储器件及其制造方法
公开(公告)号：US20100155821A1
公开(公告)日：2010-06-24
申请号：US12717076
申请日：2010-03-03
申请人： ERH-KUN LAI , HANG-TING LUE , Kuang Yeu Hsieh
发明人： ERH-KUN LAI , HANG-TING LUE , Kuang Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/792
摘要： A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.
摘要翻译：堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。该器件可以配置为NAND操作。

8. 发明申请

US20100067309A1 EFFICIENT ERASE ALGORITHM FOR SONOS-TYPE NAND FLASH 有权
标题翻译： SONOS型NAND闪存的有效擦除算法
公开(公告)号：US20100067309A1
公开(公告)日：2010-03-18
申请号：US12625438
申请日：2009-11-24
申请人： HANG-TING LUE
发明人： HANG-TING LUE
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/16
摘要： A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages.
摘要翻译：用于操作如本文所述的介电电荷捕获存储器单元的方法包括将预定电压从栅极施加到存储器单元的衬底预定时间段以减小存储器单元的阈值电压。该方法包括将来自栅极的电压序列施加到存储器单元的衬底，以进一步降低存储器单元的阈值电压，其中电压序列中的后续电压具有比栅极至衬底的量级小的电压序列中的先前电压。

9. 发明申请

US20090103367A1 ONE-TRANSISTOR CELL SEMICONDUCTOR ON INSULATOR RANDOM ACCESS MEMORY 有权
标题翻译：绝缘体随机存取存储器中的单晶硅单元半导体
公开(公告)号：US20090103367A1
公开(公告)日：2009-04-23
申请号：US12099910
申请日：2008-04-09
申请人： HANG-TING LUE
发明人： HANG-TING LUE
IPC分类号： G11C16/06 , G11C11/34 , H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/84 , H01L27/108 , H01L27/10873 , H01L27/115 , H01L27/11568 , H01L27/1203
摘要： Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide.
摘要翻译：用于非易失性实现的硅绝缘体（SOI）技术制造的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅SONOS型器件（或BE-SONOS）。可以实现超薄隧道氧化物，提供非常快的编程/擦除操作，由经典DRAM技术中使用的刷新操作支持。存储器阵列以分开的位线架构排列。栅极注入，DRAM单元被描述为没有隧道氧化物。

10. 发明申请

US20110095353A1 ONE-TRANSISTOR CELL SEMICONDUCTOR ON INSULATOR RANDOM ACCESS MEMORY 有权
标题翻译：绝缘体随机存取存储器中的单晶硅单元半导体
公开(公告)号：US20110095353A1
公开(公告)日：2011-04-28
申请号：US12940961
申请日：2010-11-05
申请人： HANG-TING LUE
发明人： HANG-TING LUE
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0466 , H01L21/84 , H01L27/108 , H01L27/10873 , H01L27/115 , H01L27/11568 , H01L27/1203
摘要： Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide.
摘要翻译：用于非易失性实现的硅绝缘体（SOI）技术制造的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅SONOS型器件（或BE-SONOS）。可以实现超薄隧道氧化物，提供非常快的编程/擦除操作，由经典DRAM技术中使用的刷新操作支持。存储器阵列以分开的位线架构排列。栅极注入，DRAM单元被描述为没有隧道氧化物。

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