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1. 发明授权

US07767525B2 Methods of forming vertical transistor structures 有权
公开(公告)号：US07767525B2
公开(公告)日：2010-08-03
申请号：US11486524
申请日：2006-07-13
申请人： H. Montgomery Manning , Kunal R. Parekh , Cem Basceri , Gurtej S. Sandhu
发明人： H. Montgomery Manning , Kunal R. Parekh , Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

2. 发明授权

US07687358B2 Methods of forming a gated device 有权
标题翻译：形成门控装置的方法
公开(公告)号：US07687358B2
公开(公告)日：2010-03-30
申请号：US11171873
申请日：2005-06-30
申请人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
发明人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

3. 发明授权

US07442977B2 Gated field effect devices 失效
标题翻译：门控场效应器件
公开(公告)号：US07442977B2
公开(公告)日：2008-10-28
申请号：US11253461
申请日：2005-10-19
申请人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
发明人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
IPC分类号： H01L27/108
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

4. 发明授权

US07846798B2 Methods of forming vertical transistor structures 有权
标题翻译：形成垂直晶体管结构的方法
公开(公告)号：US07846798B2
公开(公告)日：2010-12-07
申请号：US11486512
申请日：2006-07-13
申请人： H. Montgomery Manning , Kunal R. Parekh , Cem Basceri , Gurtej S. Sandhu
发明人： H. Montgomery Manning , Kunal R. Parekh , Cem Basceri , Gurtej S. Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
摘要翻译：本发明包括这样的方法，其中使用成角度的注入来使源极/漏极区域注入与垂直晶体管结构的天线的顶部边缘自对准。本发明还包括其中使用成角度的植入物以在垂直晶体管结构的栅极下注入掺杂剂的方法。根据本发明的方法形成的垂直晶体管结构可以结合到各种类型的集成电路中，包括例如DRAM阵列。

5. 发明授权

US07161203B2 Gated field effect device comprising gate dielectric having different K regions 有权
标题翻译：门极场效应器件包括具有不同K区域的栅极电介质
公开(公告)号：US07161203B2
公开(公告)日：2007-01-09
申请号：US10861744
申请日：2004-06-04
申请人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
发明人： Cem Basceri , H. Montgomery Manning , Gurtej S. Sandhu , Kunal R. Parekh
IPC分类号： H01L27/108
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

6. 发明申请

US20120070955A1 Methods of Forming Conductive Contacts to Source/Drain Regions and Methods of Forming Local Interconnects 有权
标题翻译：形成导电接触器到源/排放区域的方法和形成局部互连的方法
公开(公告)号：US20120070955A1
公开(公告)日：2012-03-22
申请号：US13302231
申请日：2011-11-22
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/02
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。考虑了其他方面和实现。

7. 发明授权

US07262099B2 Methods of forming field effect transistors 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US07262099B2
公开(公告)日：2007-08-28
申请号：US10925100
申请日：2004-08-23
申请人： Gurtej S. Sandhu , H. Montgomery Manning , Cem Basceri
发明人： Gurtej S. Sandhu , H. Montgomery Manning , Cem Basceri
IPC分类号： H01L21/336
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided laterally between the mass of material and the semiconductive material. The space comprises an outermost portion and a portion immediately adjacent thereto. The outermost portion has a maximum lateral width which is greater than that of the adjacent portion. Gate dielectric material and conductive gate material are formed within the space. The gate dielectric material and the conductive gate material in combination fill the adjacent portion of the space but do not fill the outermost portion of the space. At least the conductive gate material is etched from at least a majority of the outermost portion of the space. Source/drain regions are formed operatively proximate the conductive gate material and the semiconductive material is used as a channel region of the field effect transistor.
摘要翻译：一块材料形成在半导体衬底上。半导体材料横向靠近材料块形成。在材料块和半导体材料之间横向设置空间。该空间包括最外部分和与其紧邻的部分。最外侧部分的最大横向宽度大于相邻部分的宽度。栅极电介质材料和导电栅极材料形成在该空间内。栅极电介质材料和导电栅极材料组合地填充空间的相邻部分，但不填充空间的最外部分。至少导电栅极材料从空间的最外部的至少大部分被蚀刻。源极/漏极区域可操作地形成在导电栅极材料附近，并且半导体材料用作场效应晶体管的沟道区域。

8. 发明授权

US07241705B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
标题翻译：向源极/漏极区形成导电接触的方法以及形成局部互连的方法
公开(公告)号：US07241705B2
公开(公告)日：2007-07-10
申请号：US10932218
申请日：2004-09-01
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/00 , H01L21/76 , H01L21/425 , H01L21/26 , H01L21/44 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。考虑了其他方面和实现。

9. 发明授权

US08409933B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
公开(公告)号：US08409933B2
公开(公告)日：2013-04-02
申请号：US13302231
申请日：2011-11-22
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/82 , H01L21/338 , H01L21/326
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

10. 发明授权

US08084142B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
标题翻译：向源极/漏极区形成导电接触的方法以及形成局部互连的方法
公开(公告)号：US08084142B2
公开(公告)日：2011-12-27
申请号：US11525762
申请日：2006-09-21
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/44 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。考虑了其他方面和实现。

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