专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070179904A1 Apparatus and method for providing sealed storage in a data processing device 失效
标题翻译：一种用于在数据处理装置中提供密封存储的装置和方法
公开(公告)号：US20070179904A1
公开(公告)日：2007-08-02
申请号：US11345923
申请日：2006-02-02
申请人： H. Hofstee , Kanna Shimizu
发明人： H. Hofstee , Kanna Shimizu
IPC分类号： H04L9/00
CPC分类号： G06F21/57 , G06F21/6227 , G06Q20/3674 , H04L9/0897 , H04L9/32 , H04L2209/80
摘要： An apparatus and method for providing a sealed storage in a data processing device are provided. Processors of the data processing device may operate in a hardware isolation mode which allows a process to execute in an isolated environment on a processor and associated memory thereby being protected from access by other elements of the data processing device. In addition, a hardware controlled authentication and decryption mechanism is provided that is based on a hardware core key. These two features are tied together such that authentication occurs every time the isolation mode is entered. Based on the core key, which is only accessible from the hardware when in isolation mode, a chain of trust is generated by providing authentication keys for authenticating a next piece of software in the chain, in each piece of software that must be loaded, starting with the core key.
摘要翻译：提供了一种用于在数据处理设备中提供密封存储器的设备和方法。数据处理设备的处理器可以以硬件隔离模式操作，其允许过程在处理器和相关联的存储器上的隔离环境中执行，从而被数据处理设备的其他元件保护免受其访问。另外，提供了基于硬件核心密钥的硬件控制的认证和解密机制。这两个功能被绑在一起，以便每次输入隔离模式时都会进行身份验证。基于核心密钥，只有在隔离模式下才可以从硬件访问，通过提供用于认证链中的下一个软件的认证密钥，在必须加载的每个软件中，产生一个信任链，启动与核心关键。

2. 发明申请

US20070180271A1 Apparatus and method for providing key security in a secure processor 审中-公开
标题翻译：在安全处理器中提供关键安全性的装置和方法
公开(公告)号：US20070180271A1
公开(公告)日：2007-08-02
申请号：US11345848
申请日：2006-02-02
申请人： Akiyuki Hatakeyama , H. Hofstee , Kanna Shimizu
发明人： Akiyuki Hatakeyama , H. Hofstee , Kanna Shimizu
IPC分类号： G06F12/14 , H04L9/00 , H04L9/32 , G06F11/30 , G06F11/00 , G06F1/26 , G08B13/00 , G08B21/00 , G08B29/00
CPC分类号： G06F21/53 , G06F21/72 , G06F2221/2105
摘要： An apparatus and method for providing key security in a secure processor are provided. With the apparatus and method, a two-tiered key security mechanism is provided. On a first tier, a decryption mechanism and a fixed size storage area for a core key are hard-wired into the chip design. It is this first tier that is common to all systems and customers utilizing the processor design. On a second tier, off-chip but within the system is a secondary security key storage device that stores all the keys that are required by the particular system architecture. The off-chip storage device is programmed with the necessary keys before the system is shipped to the customer and thus, provides the needed flexibility. For protection, the keys are stored as an encrypted image using the core key stored on-chip.
摘要翻译：提供了一种用于在安全处理器中提供密钥安全性的装置和方法。通过该装置和方法，提供了一种双层密钥安全机制。在第一层上，用于核心密钥的解密机制和固定大小的存储区域被硬连接到芯片设计中。正是这个第一层是所有系统和客户利用处理器设计的共同之处。在第二层，片外但系统内是存储特定系统架构所需的所有密钥的辅助安全密钥存储设备。片外存储设备在系统发货给客户之前用必要的密钥进行编程，从而提供所需的灵活性。为了保护，使用存储在芯片上的核心密钥将密钥存储为加密图像。

3. 发明申请

US20070186135A1 Processor system and methodology with background error handling feature 审中-公开
标题翻译：具有背景错误处理功能的处理器系统和方法
公开(公告)号：US20070186135A1
公开(公告)日：2007-08-09
申请号：US11351121
申请日：2006-02-09
申请人： Brian Flachs , H. Hofstee , John Liberty , Brad Michael
发明人： Brian Flachs , H. Hofstee , John Liberty , Brad Michael
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A processor system is disclosed that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. ECC hardware circuitry provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The disclosed methodology permits the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The disclosed methodology provides local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.
摘要翻译：公开了一种在存储器管理电路内集成纠错码（ECC）检测和校正硬件的处理器系统。 ECC硬件电路提供与存储器数据读取和写入相结合的ECC数据位的检测，校正和生成。所公开的方法允许检测和校正从本地存储器在线读取的软单比特错误，同时使用读修改写DMA电路逻辑来校正本地存储器数据。所公开的方法在后台存储器擦除过程中提供本地存储器数据错误检测和校正，而不需要额外的在线数据逻辑。

4. 发明申请

US20070113056A1 Apparatus and method for using multiple thread contexts to improve single thread performance 审中-公开
标题翻译：使用多线程上下文来提高单线程性能的装置和方法
公开(公告)号：US20070113056A1
公开(公告)日：2007-05-17
申请号：US11274839
申请日：2005-11-15
申请人： Jason Dale , H. Hofstee , Albert Norstrand
发明人： Jason Dale , H. Hofstee , Albert Norstrand
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/3842 , G06F9/3863 , G06F9/3885
摘要： An apparatus, method and computer program product are provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.
摘要翻译：提供了一种用于使用多个线程上下文来提高单个线程的处理性能的装置，方法和计算机程序产品。当遇到异常指令时，异常指令和任何预测指令被重新加载到第一个线程上下文的缓冲区中。在遇到异常指令时，寄存器文件的状态被保存在第一个线程上下文的寄存器文件中。使用第二线程上下文中的第二寄存器文件推测地执行流水线中的指令。在推测执行期间，高速缓存未命中可能导致数据加载到缓存可能被执行。推测执行的结果将写入第二个寄存器文件。当满足停止条件时，将第一寄存器文件的内容复制到第二寄存器文件，并且重新加载的指令被释放到执行管线。

5. 发明申请

US20070113055A1 Apparatus and method for improving single thread performance through speculative processing 审中-公开
标题翻译：通过投机处理提高单线性能的装置和方法
公开(公告)号：US20070113055A1
公开(公告)日：2007-05-17
申请号：US11274838
申请日：2005-11-15
申请人： Jason Dale , H. Hofstee , Albert Norstrand
发明人： Jason Dale , H. Hofstee , Albert Norstrand
IPC分类号： G06F9/44
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3851 , G06F9/3863 , G06F9/461
摘要： An apparatus, method and computer program product are provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline.
摘要翻译：提供了一种用于使用多个线程上下文来提高单个线程的处理性能的装置，方法和计算机程序产品。当遇到异常指令时，异常指令和任何预测指令被重新加载到第一个线程上下文的缓冲区中。在遇到异常指令时，寄存器文件的状态被保存在第一个线程上下文的寄存器文件中。使用第二线程上下文中的第二寄存器文件推测地执行流水线中的指令。在推测执行期间，高速缓存未命中可能导致数据加载到缓存可能被执行。推测执行的结果将写入第二个寄存器文件。当满足停止条件时，将第一寄存器文件的内容复制到第二寄存器文件，并且重新加载的指令被释放到执行管线。

6. 发明申请

US20070043926A1 System and method for limiting the size of a local storage of a processor 失效
标题翻译：用于限制处理器的本地存储器的大小的系统和方法
公开(公告)号：US20070043926A1
公开(公告)日：2007-02-22
申请号：US11208376
申请日：2005-08-19
申请人： Adam Burns , Michael Day , Brian Flachs , H. Hofstee , Charles Johns , John Liberty
发明人： Adam Burns , Michael Day , Brian Flachs , H. Hofstee , Charles Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system and method for limiting the size of a local storage of a processor are provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统和方法。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

7. 发明申请

US20050129071A1 Highly scalable methods and apparatus for multiplexing signals 有权
标题翻译：用于复用信号的高度可扩展的方法和装置
公开(公告)号：US20050129071A1
公开(公告)日：2005-06-16
申请号：US10733694
申请日：2003-12-11
申请人： David Boerstler , Eskinder Hailu , H. Hofstee
发明人： David Boerstler , Eskinder Hailu , H. Hofstee
IPC分类号： G06F13/42 , G06F1/08 , H04J3/00 , H04L7/00 , H04J3/04
CPC分类号： H04L7/0083 , G06F1/08
摘要： In a first aspect, a first method is provided that includes providing a plurality of select signals and a plurality of input signals for input by a multiplexer. Each select signal is adapted to cause the multiplexer to select a different one of the plurality of input signals for output by the multiplexer when the select signal is in a first logic state. The first method further includes preventing a first of the select signals that is in the first logic state from being provided to the multiplexer until the other select signals are in a second logic state. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种第一方法，其包括提供多个选择信号和多个输入信号以供多路复用器输入。当选择信号处于第一逻辑状态时，每个选择信号适于使多路复用器选择多个输入信号中的不同的一个以供多路复用器输出。第一种方法还包括防止处于第一逻辑状态的第一选择信号被提供给多路复用器，直到其他选择信号处于第二逻辑状态。提供了许多其他方面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式