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    • 1. 发明申请
    • DIGITAL PHASE-LOCKED LOOP WITH REDUCED LOOP DELAY
    • 数字相位锁定环路,减少环路延迟
    • US20110133795A1
    • 2011-06-09
    • US12790242
    • 2010-05-28
    • Gyu Suck KIMSeong Hwan CHOWoo Kon SON
    • Gyu Suck KIMSeong Hwan CHOWoo Kon SON
    • H03L7/08
    • H03L7/1806H03L2207/50
    • There is provided a digital phase-locked loop. A digital phase-locked loop according to an aspect of the invention may include: a reference phase accumulation unit outputting a reference sampling phase value; a phase detection unit detecting a phase difference signal; a digital loop filter filtering and averaging the phase difference signal from the phase detection unit; a digitally controlled oscillator generating an oscillation signal having a predetermined frequency; a DOC phase accumulation unit outputting the DCO sampling phase value, and generating a plurality of first to n-th D-FFs having the same frequency and different phases delayed in a sequential manner; and first to n-th D-FFs included in a closed loop including the phase detection unit, the digital loop filter, the digitally controlled oscillator, and the DOC phase accumulation unit, and operating according to the plurality of first to n-th clock signals from the DCO phase accumulation unit, respectively.
    • 提供了数字锁相环。 根据本发明的一个方面的数字锁相环可以包括:参考相位累积单元,输出参考采样相位值; 检测相位差信号的相位检测单元; 数字环路滤波器对来自相位检测单元的相位差信号进行滤波和平均; 产生具有预定频率的振荡信号的数字控制振荡器; DOC相位累积单元输出DCO采样相位值,并且产生具有以相继方式延迟的相同频率和不同相位的多个第一至第n个D-FF; 以及包括在相位检测单元,数字环路滤波器,数字控制振荡器和DOC相位累积单元的闭环中的第一至第N-D-FF,并且根据多个第一至第n时钟 分别来自DCO相位累积单元的信号。