专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090035919A1 IN-PLACE BONDING OF MICROSTRUCTURES 失效
标题翻译：微结构的位置结合
公开(公告)号：US20090035919A1
公开(公告)日：2009-02-05
申请号：US12248941
申请日：2008-10-10
申请人： Guy Moshe Cohen , Patricia M. Mooney , Vamsi K. Paruchuri
发明人： Guy Moshe Cohen , Patricia M. Mooney , Vamsi K. Paruchuri
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L24/26 , H01L24/83 , H01L25/16 , H01L2224/8385 , H01L2224/83894 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/01072 , H01L2924/0132 , H01L2924/07802 , H01L2924/1306 , H01L2924/13091 , H01L2924/01014 , H01L2924/00
摘要： A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the micro-slabs is also referred to herein as “in-place bonding”. Semiconductor structures which include the attractively bonded microstructures and substrate are also disclosed.
摘要翻译：提供了使用吸引力（例如疏水性，范德华氏）和共价键将微结构结合到半导体衬底的方法。微结构保持彼此的绝对位置，并且在接合过程中将其垂直平移到晶片表面上。微板的垂直平移在本文中也称为“就地结合”。还公开了包括具有吸引力的微结构和衬底的半导体结构。

2. 发明授权

US07238589B2 In-place bonding of microstructures 失效
标题翻译：微结构的就地结合
公开(公告)号：US07238589B2
公开(公告)日：2007-07-03
申请号：US10978551
申请日：2004-11-01
申请人： Guy Moshe Cohen , Patricia M. Mooney , Vamsi K. Paruchuri
发明人： Guy Moshe Cohen , Patricia M. Mooney , Vamsi K. Paruchuri
IPC分类号： H01L21/58
CPC分类号： H01L25/50 , H01L24/26 , H01L24/83 , H01L25/16 , H01L2224/8385 , H01L2224/83894 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/01072 , H01L2924/0132 , H01L2924/07802 , H01L2924/1306 , H01L2924/13091 , H01L2924/01014 , H01L2924/00
摘要： A method for bonding microstructures to a semiconductor substrate using attractive forces, such as, hydrophobic, van der Waals, and covalent bonding is provided. The microstructures maintain their absolute position with respect to each other and translate vertically onto a wafer surface during the bonding process. The vertical translation of the micro-slabs is also referred to herein as “in-place bonding”. Semiconductor structures which include the attractively bonded microstructures and substrate are also disclosed.
摘要翻译：提供了使用吸引力（例如疏水性，范德华氏）和共价键将微结构结合到半导体衬底的方法。微结构保持彼此的绝对位置，并且在接合过程中将其垂直平移到晶片表面上。微板的垂直平移在本文中也称为“就地结合”。还公开了包括具有吸引力的微结构和衬底的半导体结构。

3. 发明申请

US20090124092A1 METHODS OF SELECTIVE DEPOSITION OF FINE PARTICLES ONTO SELECTED REGIONS OF A SUBSTRATE 失效
标题翻译：精选颗粒选择性沉积在基材选择区域的方法
公开(公告)号：US20090124092A1
公开(公告)日：2009-05-14
申请号：US12352290
申请日：2009-01-12
申请人： Guy Moshe Cohen
发明人： Guy Moshe Cohen
IPC分类号： H01L21/30
CPC分类号： H01L21/288 , H01L21/7685 , H01L21/76852 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L2221/1094
摘要： A method for depositing fine particles from a suspension on selected regions of a substrate is disclosed. The particles are deposited on selected regions of a clean hydrophobic semiconductor surface that are surrounded by a wetting boundary which includes a mesa formed by etching through a silicon-on-insulator (SOI) film and an underlying buried oxide of an SOI substrate. The process is well suited for the growth of semiconductor nanowires that nucleates from fine particle used as a catalyst.
摘要翻译：公开了一种从悬浮液在衬底的选定区域上沉积细颗粒的方法。颗粒沉积在干净的疏水性半导体表面的被润湿边界包围的选定区域上，润湿边界包括通过蚀刻通过绝缘体上硅（SOI）膜和SOI衬底的下层掩埋氧化物形成的台面。该方法非常适用于从用作催化剂的细颗粒成核的半导体纳米线的生长。

4. 发明申请

US20080191317A1 SELF-ALIGNED EPITAXIAL GROWTH OF SEMICONDUCTOR NANOWIRES 审中-公开
标题翻译：自对准的半导体纳米粒子的外延生长
公开(公告)号：US20080191317A1
公开(公告)日：2008-08-14
申请号：US11674453
申请日：2007-02-13
申请人： Guy Moshe Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
发明人： Guy Moshe Cohen , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/0665 , B82Y10/00 , C30B11/12 , C30B29/60 , H01L21/0237 , H01L21/02381 , H01L21/02521 , H01L21/02603 , H01L21/02639 , H01L21/02642 , H01L21/02645 , H01L21/02653 , H01L21/28525 , H01L29/0673 , H01L29/0676 , H01L2221/1094
摘要： Disclosed herein is a method of forming a nanostructure having nanowires by forming a mask with at least one opening on a surface of a substrate, to expose a portion of the surface of the substrate; depositing particles of a metal capable of catalyzing semiconductor nanowire growth on the exposed surface of the substrate by electroplating or electroless plating; and growing nanowires on the plated substrate with a precursor gas by a vapor-liquid-solid (VLS) process. Also disclosed is a nanostructure including nanowires prepared by the above method.
摘要翻译：本文公开了一种通过在衬底的表面上形成具有至少一个开口的掩模来形成具有纳米线的纳米结构的方法，以暴露衬底表面的一部分; 通过电镀或化学电镀将能够催化半导体纳米线生长的金属的颗粒沉积在基板的暴露表面上; 并通过气 - 液 - 固（VLS）工艺在具有前体气体的电镀衬底上生长纳米线。还公开了包括通过上述方法制备的纳米线的纳米结构。

5. 发明授权

US07336863B2 Apparatus and methods for integrally packaging optoelectronic devices, IC chips and optical transmission lines 有权
标题翻译：用于整体封装光电器件，IC芯片和光传输线的装置和方法
公开(公告)号：US07336863B2
公开(公告)日：2008-02-26
申请号：US11257904
申请日：2005-10-25
申请人： Guy Moshe Cohen , Fuad Elias Doany , Jeannine M. Trewhella
发明人： Guy Moshe Cohen , Fuad Elias Doany , Jeannine M. Trewhella
IPC分类号： G02B6/12
CPC分类号： B29D11/0075 , G02B6/42 , G02B6/4224 , G02B6/423 , G02B6/4249
摘要： Apparatus and methods for packaging optical communication devices include optical bench structures, such as silicon-optical benches (SiOB). An optical communications apparatus includes an optical bench comprising a substrate having an electrical turning via formed therein. An optoelectronic (OE) chip and integrated circuit (IC) chip are mounted on the optical bench and electrically connected using the electrical turning via. The electrical turning via extends in directions both perpendicular and transverse to a surface of the substrate such that the OE chip and IC chip can be mounted on perpendicular surfaces of the optical bench in close proximity and electrically connected using the electrical turning via. More specifically, the OE chip and IC chip are mounted on the optical bench such that a light-emitting or light-detecting surface of the OE chip is substantially perpendicular to a surface of the IC chip having contacts, and such that optical transmission lines that are mounted parallel to the substrate surface can be directly coupled to the OE chip.
摘要翻译：用于封装光通信设备的装置和方法包括光学台架结构，例如硅光学台（SiOB）。一种光通信设备包括一个光学台，包括一个具有形成在其中的电转通路的基板。光电（OE）芯片和集成电路（IC）芯片安装在光学平台上，并使用电动转向电路进行电气连接。电动转向通孔在垂直于基板表面的横向方向上延伸，使得OE芯片和IC芯片可以安装在光学平台的垂直表面上，并且使用电动转向电路进行电连接。更具体地，OE芯片和IC芯片安装在光学平台上，使得OE芯片的发光或光检测表面基本上垂直于具有触点的IC芯片的表面，并且使得光传输线平行于衬底表面安装可以直接耦合到OE芯片。

6. 发明授权

US06690072B2 Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device 有权
标题翻译：通过垂直自对准COSI2在升高的源极漏极Si / SiGe器件上形成的超低接触电阻CMOS的方法和结构
公开(公告)号：US06690072B2
公开(公告)日：2004-02-10
申请号：US10156782
申请日：2002-05-24
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Kevin K. Chan , Jack O. Chu , Guy Moshe Cohen , Steven J. Koester , Christian Lavoie , Ronnen A. Roy
IPC分类号： H01L2904
CPC分类号： H01L29/41783 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/161 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.
摘要翻译：形成垂直自对准的硅化物接触到下面的SiGe层的方法（和结构）包括在SiGe层上形成第一预定厚度的硅层，并在硅层上形成一层金属，其中金属层具有第二预定厚度。然后在预定温度下的热退火工艺形成硅和金属的硅化物，其中选择预定温度以基本排除硅化物渗透到下面的SiGe层中。

7. 发明授权

US07915685B2 Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates 有权
标题翻译：应变通道鳍状场效应晶体管（FET）具有均匀的沟道厚度和分离的栅极
公开(公告)号：US07915685B2
公开(公告)日：2011-03-29
申请号：US11927801
申请日：2007-10-30
申请人： Guy Moshe Cohen
发明人： Guy Moshe Cohen
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/7842 , H01L29/78687 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.
摘要翻译：半导体器件（及其制造方法）包括邻近源极和漏极形成的应变硅沟道，在沟道的第一侧上形成的第一栅极，在沟道的第二侧上形成的第二栅极，形成在第一栅极和应变硅沟道之间的第一栅极电介质，以及形成在第二栅极和应变硅沟道之间的第二栅极电介质。应变硅通道是非平面的。

8. 发明授权

US07842562B2 Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates 有权
标题翻译：应变通道鳍状场效应晶体管（FET）具有均匀的沟道厚度和分离的栅极
公开(公告)号：US07842562B2
公开(公告)日：2010-11-30
申请号：US11927893
申请日：2007-10-30
申请人： Guy Moshe Cohen
发明人： Guy Moshe Cohen
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/7842 , H01L29/78687 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.
摘要翻译：半导体器件（及其制造方法）包括邻近源极和漏极形成的应变硅沟道，在沟道的第一侧上形成的第一栅极，在沟道的第二侧上形成的第二栅极，形成在第一栅极和应变硅沟道之间的第一栅极电介质，以及形成在第二栅极和应变硅沟道之间的第二栅极电介质。应变硅通道是非平面的。

9. 发明申请

US20090309160A1 STRAINED-SILICON-ON-INSULATOR SINGLE-AND DOUBLE-GATE MOSFET AND METHOD FOR FORMING THE SAME 失效
标题翻译：应变硅绝缘体单和双栅MOSFET及其形成方法
公开(公告)号：US20090309160A1
公开(公告)日：2009-12-17
申请号：US12544431
申请日：2009-08-20
申请人： Guy Moshe Cohen , Patricia May Mooney
发明人： Guy Moshe Cohen , Patricia May Mooney
IPC分类号： H01L27/12 , H01L21/762 , G06F17/50
CPC分类号： H01L29/7842 , H01L21/76264 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： A method of forming a semiconductor structure (and the resulting structure), includes straining a free-standing semiconductor, and fixing the strained, free-standing semiconductor to a substrate.
摘要翻译：形成半导体结构（及其结构）的方法包括使自立式半导体变形，将应变的自立式半导体固定在基板上。

10. 发明授权

US07355253B2 Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates 有权
公开(公告)号：US07355253B2
公开(公告)日：2008-04-08
申请号：US10645646
申请日：2003-08-22
申请人： Guy Moshe Cohen
发明人： Guy Moshe Cohen
IPC分类号： H01L23/62
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823487 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/66795 , H01L29/7842 , H01L29/78687 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric formed between the first gate and the strained-silicon channel, and a second gate dielectric formed between the second gate and the strained-silicon channel. The strained-silicon channel is non-planar.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式