专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100221920A1 SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES 有权
标题翻译：用于触点接触和相关结构的间隔工艺
公开(公告)号：US20100221920A1
公开(公告)日：2010-09-02
申请号：US12781681
申请日：2010-05-17
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。还公开了与该方法相关联的结构。在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。互连可以由间距倍增形成。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。可选择定义的材料中的特征被修剪到期望的尺寸。间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料以留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

2. 发明授权

US08772166B2 Spacer process for on pitch contacts and related structures 有权
标题翻译：间距接触和相关结构的间隔过程
公开(公告)号：US08772166B2
公开(公告)日：2014-07-08
申请号：US13526792
申请日：2012-06-19
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了包括用于增加集成电路中的隔离特征的密度的方法。还公开了相关联的结构。在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料，留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

3. 发明授权

US08211803B2 Spacer process for on pitch contacts and related structures 有权
标题翻译：间距接触和相关结构的间隔过程
公开(公告)号：US08211803B2
公开(公告)日：2012-07-03
申请号：US12781681
申请日：2010-05-17
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。还公开了与该方法相关联的结构。在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。互连可以由间距倍增形成。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。可选择定义的材料中的特征被修剪到期望的尺寸。间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料以留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

4. 发明申请

US20090115064A1 SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES 有权
标题翻译：用于触点接触和相关结构的间隔工艺
公开(公告)号：US20090115064A1
公开(公告)日：2009-05-07
申请号：US11933664
申请日：2007-11-01
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L23/52 , H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。还公开了与该方法相关联的结构。在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。互连可以由间距倍增形成。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。可选择定义的材料中的特征被修剪到期望的尺寸。间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料以留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

5. 发明申请

US20120258599A1 SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES 有权
标题翻译：用于触点接触和相关结构的间隔工艺
公开(公告)号：US20120258599A1
公开(公告)日：2012-10-11
申请号：US13526792
申请日：2012-06-19
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了包括用于增加集成电路中的隔离特征的密度的方法。还公开了相关联的结构。在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料，留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

6. 发明授权

US07737039B2 Spacer process for on pitch contacts and related structures 有权
标题翻译：间距接触和相关结构的间隔过程
公开(公告)号：US07737039B2
公开(公告)日：2010-06-15
申请号：US11933664
申请日：2007-11-01
申请人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
发明人： Gurtej Sandhu , Mark Kiehlbauch , Steve Kramer , John Smythe
IPC分类号： H01L21/311
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L23/528 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.
摘要翻译：公开了诸如涉及增加集成电路中的隔离特征的密度的方法。还公开了与该方法相关联的结构。在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。互连可以由间距倍增形成。为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。可选择定义的材料中的特征被修剪到期望的尺寸。间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。去除可选择定义的材料以留下由间隔物材料限定的掩模。由间隔物材料限定的图案可以转移到基底上，以形成间距接触。在一些实施例中，上电触点可用于电接触衬底中的导电互连。

7. 发明授权

US08637113B2 Methods of forming a non-volatile resistive oxide memory array 有权
标题翻译：形成非易失性电阻氧化物存储器阵列的方法
公开(公告)号：US08637113B2
公开(公告)日：2014-01-28
申请号：US13354163
申请日：2012-01-19
申请人： Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
发明人： Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
IPC分类号： C23C18/00 , C23C20/00 , C23C28/00 , C23C30/00 , H01C17/06
CPC分类号： H01L27/101 , H01L21/0271 , Y10S438/947
摘要： A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.
摘要翻译：形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。含金属氧化物的材料形成在多条所述一条字线或位线中。在多个所述一条字线或位线之间提供一系列细长的沟槽。多个自组装嵌段共聚物线形成在沟槽中的各个内，与沟槽侧壁之间对准并且在沟槽侧壁之间形成。从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线，以形成包含所述金属氧化物的材料的单独可编程的结，其中字线和位线彼此交叉。

8. 发明申请

US20130005143A1 METHOD AND APPARATUS PROVIDING AIR-GAP INSULATION BETWEEN ADJACENT CONDUCTORS USING NANOPARTICLES 有权
标题翻译：在使用纳米颗粒的相邻导体之间提供空气隙绝缘的方法和装置
公开(公告)号：US20130005143A1
公开(公告)日：2013-01-03
申请号：US13616080
申请日：2012-09-14
申请人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
发明人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
IPC分类号： H01L21/28 , B82Y40/00
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.
摘要翻译：公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

9. 发明授权

US08034655B2 Non-volatile resistive oxide memory cells, non-volatile resistive oxide memory arrays, and methods of forming non-volatile resistive oxide memory cells and memory arrays 有权
标题翻译：非易失性电阻氧化物存储单元，非易失性电阻氧化物存储器阵列以及形成非易失性电阻氧化物存储器单元和存储器阵列的方法
公开(公告)号：US08034655B2
公开(公告)日：2011-10-11
申请号：US12099267
申请日：2008-04-08
申请人： John Smythe , Bhaskar Srinivasan , Gurtej Sandhu
发明人： John Smythe , Bhaskar Srinivasan , Gurtej Sandhu
IPC分类号： H01L21/8239
CPC分类号： H01L45/04 , G11C11/56 , G11C13/00 , H01L27/2463 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.
摘要翻译：形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。绝缘材料沉积在第一电极上。在第一电极上形成绝缘材料的开口。开口包括侧壁和底座。开口侧壁和基底衬有包含少于填充开口的多电阻态金属氧化物材料的多电阻状态层。存储单元的第二导电电极形成在多个电阻状态层的横向内侧的开口的内部，该电阻层衬在侧壁上，并且在衬底基底上的多电阻状态层的顶部形成。考虑了其他方面和实现。

10. 发明申请

US20110201211A1 Method and Apparatus Providing Air-Gap Insulation Between Adjacent Conductors Using Nanoparticles 有权
标题翻译：使用纳米颗粒在相邻导体之间提供空气间隙绝缘的方法和装置
公开(公告)号：US20110201211A1
公开(公告)日：2011-08-18
申请号：US13096052
申请日：2011-04-28
申请人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
发明人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
IPC分类号： H01L21/31 , B82Y40/00
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.
摘要翻译：公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式