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1. 发明授权

US5841315A Matched filter circuit 失效
标题翻译：匹配滤波电路
公开(公告)号：US5841315A
公开(公告)日：1998-11-24
申请号：US686958
申请日：1996-07-26
申请人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Xiaoling Qin , Shengmin Lin , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Xiaoling Qin , Shengmin Lin , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03M1/66 , H03H11/04 , H03H17/02 , H03H19/00 , H03M3/02 , H03K5/00 , G11C27/02 , H03K12/00
CPC分类号： H04B1/7093 , H03H11/04 , H03H17/0254 , H04B1/7117
摘要： An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.
摘要翻译：本发明的目的是提供一种尺寸小且消耗低功率的匹配滤波电路。注意扩展码是1位数据串，输入信号被采样并保持为沿着时间序列的模拟信号，分为“1”和“-1”，分类信号通过电容耦合并联在根据本发明的匹配滤波器电路中。

2. 发明授权

US06169771A Matched filter for spread spectrum communication systems and hybrid analog-digital transversal filter 失效
标题翻译：用于扩频通信系统和混合模数转换滤波器的匹配滤波器
公开(公告)号：US06169771A
公开(公告)日：2001-01-02
申请号：US09014264
申请日：1998-01-27
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H04L2706
CPC分类号： H03H17/0254 , H04B1/7093
摘要： In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.
摘要翻译：一方面，本发明提供一种低功耗匹配滤波器。在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。通过移位寄存器中的系数来防止采样数据传输错误存储。采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。加法电路以相同的方式刷新。

3. 发明授权

US5958002A Vector absolute--value calculation circuit 失效
标题翻译：矢量绝对值计算电路
公开(公告)号：US5958002A
公开(公告)日：1999-09-28
申请号：US905784
申请日：1997-08-12
申请人： Changming Zhou , Guoliang Shou , Kunihiko Suzuki , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Changming Zhou , Guoliang Shou , Kunihiko Suzuki , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： G06G7/25 , G06G7/22 , G06G7/00 , G06G7/16
CPC分类号： G06G7/22
摘要： A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27. ##EQU1##
摘要翻译：高精度矢量绝对值计算电路采用模拟处理和最小硬件。对应于I分量（实数部分）和Q分量（虚数部分）的信号电压分别通过端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，以及它们都被转换为绝对值信号。在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值通过控制多路复用器21和22将信号输出到输入电容器24.神经计算电路和输入电容器23和24的反馈电容器26的容量比为11:10:5。从输出端子27输出由下式计算的复数绝对值。

4. 发明授权

US5815021A Weight addition circuit 失效
标题翻译：加权电路
公开(公告)号：US5815021A
公开(公告)日：1998-09-29
申请号：US686761
申请日：1996-07-26
申请人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： G06G7/14 , G06J1/00 , G06G7/16
CPC分类号： G06J1/00 , G06G7/14
摘要： The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.
摘要翻译：本发明提供一种加权加法电路，用于通过比传统电路小的电路进行采样，保持和执行加权相加。在本发明的加权加法电路中，电容耦合连接到多个开关，该开关进一步仅与输入电压相连。在电容耦合中保持电压并加上重量。

5. 发明授权

US5748510A Multiplication circuit with serially connected capacitive couplings 失效
标题翻译：具有串联电容耦合的乘法电路
公开(公告)号：US5748510A
公开(公告)日：1998-05-05
申请号：US536244
申请日：1995-09-29
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： G06G7/16 , G06J1/00
CPC分类号： G06J1/00
摘要： A multiplication circuit includes a plurality of switches which receive a common analog input voltage and a reference voltage and which alternatively output the input voltage or the reference voltage. A first capacitive coupling is provided which has a plurality of capacitors, each of which receives an output from a respective switch, and a second capacitive coupling is provided with a plurality of capacitors, each of which likewise receives an output from a respective switch. One or more of the capacitors in the first capacitive coupling is connected to the second capacitive coupling. A first inverted amplifier and a second inverted amplifier are connected in series to the output of the second capacitive coupling with individual feedback.
摘要翻译：乘法电路包括多个开关，其接收公共模拟输入电压和参考电压，并且输出输入电压或参考电压。提供了第一电容耦合，其具有多个电容器，每个电容器接收来自相应开关的输出，并且第二电容耦合提供有多个电容器，每个电容器同样接收来自相应开关的输出。第一电容耦合中的一个或多个电容器连接到第二电容耦合。第一反相放大器和第二反相放大器与具有各个反馈的第二电容耦合的输出串联连接。

6. 发明授权

US5734583A Capacitance forming method 失效
标题翻译：电容成型法
公开(公告)号：US5734583A
公开(公告)日：1998-03-31
申请号：US536326
申请日：1995-09-29
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H01L27/08 , H01L27/10 , G06F17/50
CPC分类号： H01L27/0805 , H01L27/101
摘要： A capacitance forming method for forming capacitances corresponding to a plurality of constant numbers within a large scale integrated circuit (LSI) comprises steps of defining a unit capacitance with a predetermined shape, defining an arrangement of a plurality of the unit capacitances of a number necessary for total capacity of capacitances to be formed in two dimension in an area of the LSI, selecting the unit capacitances of a number corresponding to the maximal capacity among capacities of the capacitances to be formed so that the selected unit capacitances are equivalently dispersed over the area, and successively selecting other of the capacitances than the capacitance of the maximal capacity in the order of capacities, and selecting the unit capacitances of a number corresponding to a capacity of each the capacitance selected so that the selected unit capacitances are equivalently dispersed over an area of the rest of the unit capacitances which have not selected yet.
摘要翻译：用于在大规模集成电路（LSI）内形成对应于多个常数的电容的电容形成方法包括以预定形状定义单位电容的步骤，限定多个单位电容的排列，在LSI的区域中形成二维电容的总容量，选择与要形成的电容的容量之间的最大容量相对应的数字的单位电容，使得所选择的单位电容等效地分散在该区域上，并且依次选择电容量以及容量顺序的最大容量的电容量，并且选择与所选择的每个电容的容量对应的数量的单位电容，使得所选择的单位电容等价地分散在其余单位电容尚未选择。

7. 发明授权

US5917343A MOS inverter circuit 失效
标题翻译： MOS逆变电路
公开(公告)号：US5917343A
公开(公告)日：1999-06-29
申请号：US922680
申请日：1997-09-03
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H01L27/02 , H01L27/07 , H01L27/092 , H03K19/003 , H03K19/0948 , H01L27/00
CPC分类号： H01L27/0705 , H01L27/0203 , H01L27/0207 , H01L27/092 , H03K19/00384 , H01L2924/0002
摘要： A MOS inverter within a large scale integrated circuit (LSI) includes a pair of circuits with the same performance. Each of the circuits includes a plurality of MOS inverters serially connected from the first stage to the last stage. Each of the MOS inverters is provided with an input such that the input of the MOS inverters of the first stage are formed to be adjacent one another.
摘要翻译：大规模集成电路（LSI）中的MOS反相器包括具有相同性能的一对电路。每个电路包括从第一级到最后级串联连接的多个MOS反相器。每个MOS反相器具有输入，使得第一级的MOS反相器的输入形成为彼此相邻。

8. 发明授权

US5661482A Interface circuit having a plurality of thresholding circuits 失效
标题翻译：接口电路具有多个阈值电路
公开(公告)号：US5661482A
公开(公告)日：1997-08-26
申请号：US536243
申请日：1995-09-29
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03M1/34 , G06J1/00 , H03M1/74 , H03K19/0175 , H03K19/00
CPC分类号： G06J1/00
摘要： An interface circuit comprising a digital to analog converter which comprises a register for receiving and holding each bit of a digital signal, a capacitive coupling for integrating total bits held in the register with weighting, an inverted amplifier circuit for receiving an output of the capacitive coupling and for outputting an analog output voltage, and a feedback capacitance for connecting an outputs of the inverted amplifier circuit to an input of the inverted amplifier circuit, an analog signal line to which the analog output voltage is connected, and an analog to digital converter which comprises a plurality thresholding circuits with stepwise thresholds to which the analog signal line is commonly inputted, each the thresholding circuit receiving outputs of the thresholding circuits of higher threshold with weighting so that the thresholding circuits repeatedly change the outputs from high level to low level or from low level to high level.
摘要翻译：一种接口电路，包括数模转换器，其包括用于接收和保持数字信号的每一位的寄存器，用于将保持在寄存器中的总比特积分为加权的电容耦合，反相放大器电路，用于接收电容耦合的输出并且用于输出模拟输出电压，以及用于将反相放大器电路的输出连接到反相放大器电路的输入的反馈电容，连接有模拟输出电压的模拟信号线以及模数转换器，包括具有逐步阈值的多个阈值电路，模拟信号线被共同地输入到该阈值电路中，每个阈值电路通过加权接收具有较高阈值的阈值电路的输出，使得阈值电路将输出从高电平重复地改变为低电平或从低级到高级。

9. 发明授权

US5606274A Sampling and holding circuit 失效
标题翻译：取样保持电路
公开(公告)号：US5606274A
公开(公告)日：1997-02-25
申请号：US512317
申请日：1995-08-08
申请人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： G11C27/02
CPC分类号： G11C27/026 , G11C27/024
摘要： An analog input voltage is inputted to a first sample and hold circuit and a second sample and hold circuit is connected to an output of the first sample and hold circuit. The output of the first and second sample and hold circuits are inputted to a multiplexer which alternatively outputs the output of first sample and hold circuit or the second sample and hold circuit. When one of the first and second sample and hold circuits is refreshed, the output of the other sample and hold circuit is selected to be outputted from the multiplexer.
摘要翻译：模拟输入电压被输入到第一采样保持电路，第二采样和保持电路连接到第一采样和保持电路的输出。第一和第二采样和保持电路的输出被输入到多路复用器，该多路复用器交替地输出第一采样保持电路或第二采样和保持电路的输出。当第一和第二取样和保持电路中的一个被刷新时，另一采样和保持电路的输出被选择为从多路复用器输出。

10. 发明授权

US5789962A Multiplication circuit 失效
标题翻译：乘法电路
公开(公告)号：US5789962A
公开(公告)日：1998-08-04
申请号：US638330
申请日：1996-04-26
申请人： Guoliang Shou , Kazunori Motohashi , Jian Luo , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Kazunori Motohashi , Jian Luo , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06J1/00 , G06F7/44
CPC分类号： G06J1/00
摘要： A multiplication circuit has two capacitive couplings connected first and second inverting amplifiers, respectively. Two steps of multiplication are performed by this circuit. Input is multiplied by a multiplier of a product of multipliers of the successive multiplication circuits, so the total multiplier can be rather large with similar capacitances to that of the conventional circuit.
摘要翻译：乘法电路分别具有连接第一和第二反相放大器的两个电容耦合。该电路执行两步乘法运算。输入乘以连续乘法电路的乘法乘积乘法器，因此与常规电路的乘法电容相似，总乘法器可能相当大。

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