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1. 发明授权

US07227379B1 Nanoscale latch-array processing engines 有权
标题翻译：纳米级闩锁阵列处理引擎
公开(公告)号：US07227379B1
公开(公告)日：2007-06-05
申请号：US11192197
申请日：2005-07-27
申请人： Gregory S. Snider , Philip J. Kuekes , Duncan R. Stewart
发明人： Gregory S. Snider , Philip J. Kuekes , Duncan R. Stewart
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： B82Y10/00 , G06N99/007 , H01L27/101
摘要： One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions. Nanoscale-latch arrays can be combined and interconnected in an almost limitless number of different ways to construct arbitrarily complex, sequential, parallel, or both parallel and sequential computing engines that represent additional embodiments of the present invention.
摘要翻译：本发明的一个实施例是通过纳米线总线互连以形成锁存阵列的纳米级锁存器的阵列。纳米尺度锁存阵列中的每个纳米级锁存器用作纳米尺度寄存器，并由纳米尺度控制线驱动。锁存阵列的原始操作可以被定义为一个或多个输入到纳米线数据总线和纳米尺度控制线中的一个或多个的序列。在本发明的各种锁存阵列实施例中，可以以受控的方式将信息从一个纳米级锁存器传送到另一个纳米级锁存器，并且可以设计信息传输操作的序列以实现任意的布尔逻辑运算，并且运算符包括NOT， AND，OR，XOR，NOR，NAND和其他这样的布尔逻辑运算符和操作，以及输入和输出功能。纳秒级锁存器阵列可以以几乎无限数量的不同方式组合和互连，以构造代表本发明附加实施例的任意复杂，顺序，并行或并行和顺序的计算引擎。

2. 发明授权

US07609089B2 FPGA architecture at conventional and submicron scales 有权
标题翻译：常规和亚微米尺度的FPGA架构
公开(公告)号：US07609089B2
公开(公告)日：2009-10-27
申请号：US12156877
申请日：2008-06-04
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17748 , B82Y10/00 , B82Y30/00 , G11C8/10 , G11C13/0007 , G11C13/0014 , G11C2213/15 , G11C2213/34 , G11C2213/51 , G11C2213/77 , G11C2213/81 , H03K19/17728 , H03K19/1778
摘要： Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.
摘要翻译：公开了可重构逻辑器件和编程器件的方法。逻辑器件包括查找表（LUT）和配置用于对LUT输出信号进行采样的至少一个存储元件。 LUT包括多个输入信号，可操作地耦合到输入信号的可编程阻抗装置的阵列和LUT输出信号。阵列中的每个可编程阻抗器件包括可操作地耦合到输入信号中的一个的第一电极，设置成形成其中第二电极至少部分地与第一电极重叠的结的第二电极和设置在第一电极和第二电极。可编程材料可操作地耦合第一电极和第二电极，使得每个可编程阻抗装置呈现非易失性可编程阻抗。该阵列可以被配置为一维或二维阵列。

3. 发明授权

US07652911B2 Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers 有权
标题翻译：使用微米/纳米级移位寄存器的纳米级移位寄存器和信号解复用
公开(公告)号：US07652911B2
公开(公告)日：2010-01-26
申请号：US12331642
申请日：2008-12-10
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0023 , G11C19/00 , G11C2213/17 , G11C2213/77 , G11C2213/81
摘要： Methods for inputting a data-value pattern into a nanowire crossbar, for inputting a data-value pattern into a nanowire crossbar that support computer instructions stored in a computer-readable medium, and for distributing a received data value to each of a set of nanowires that support control logic implemented in logic circuits are provided. First and second nanoscale shift registers are employed, the first having output signal lines that form or interconnect with a first parallel set of nanowire-crossbar nanowires and the second having output signal lines that form or interconnect with a second parallel set of nanowire-crossbar nanowires. A first pattern of values is stored in the first shift register and a second pattern of values is stored in the second shift register using voltage signals below the WRITE voltage for junctions of the crossbar. Voltage signals greater than or equal to the WRITE threshold are applied for junctions of the crossbar to write the pattern of data values into the crossbar.
摘要翻译：用于将数据值图案输入到纳米线交叉开关中的方法，用于将数据值图案输入到支持存储在计算机可读介质中的计算机指令的纳米线交叉开关中，以及用于将接收到的数据值分配到一组纳米线中的每一个提供了在逻辑电路中实现的支持控制逻辑。采用第一和第二纳米级移位寄存器，第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度移位寄存器，其中第一和第二纳米尺度的移动寄存器，。值的第一模式被存储在第一移位寄存器中，并且第二模式的值被存储在第二移位寄存器中，该电压信号低于用于交叉开关的接点的写电压。施加大于或等于WRITE阈值的电压信号用于交叉开关的交叉点，以将数据值的模式写入交叉开关。

4. 发明授权

US07436209B1 Nanoscale electronic latch 有权
标题翻译：纳米级电子锁
公开(公告)号：US07436209B1
公开(公告)日：2008-10-14
申请号：US11590491
申请日：2006-10-30
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/177
CPC分类号： H01L27/10 , B82Y10/00 , H01L29/0665 , H01L29/0673
摘要： In one embodiment of the present invention, a nanoscale latch is implemented by interconnecting an enable line, two control lines, and a pull-down line, when needed, to a signal line carrying encoded binary values to be latched and subsequently output. The enable line is interconnected with the signal line through a field-effect-transistor-like nanoscale junction. Both control lines are interconnected with the signal line through asymmetric-switch nanoscale junctions of like polarities. The pull-down line, when needed, is interconnected with the signal line through a resistive nanoscale junction. Inputting a sequence of signals to the enable and control lines allows a value input from the signal line to be stored and subsequently output to the signal line. In various additional embodiments, an array of nanoscale latches can be implemented by overlaying enable and control lines, and a pull-down line when needed, over a set of parallel nanowires.
摘要翻译：在本发明的一个实施例中，纳米尺度锁存器通过在需要时将使能线，两条控制线和下拉线互连到一个承载要锁存并随后输出的编码二进制值的信号线来实现。使能线通过场效应晶体管状纳米级结与信号线互连。两个控制线通过具有相似极性的非对称开关纳米级结与信号线互连。当需要时，下拉线通过电阻性纳米级结与信号线互连。将一系列信号输入到使能和控制线路允许从信号线输入的值被存储并随后输出到信号线。在各种附加实施例中，纳米尺度锁存器的阵列可以通过在一组平行纳米线上覆盖使能和控制线以及需要时的下拉线来实现。

5. 发明授权

US07307448B2 Interconnectable nanoscale computational stages 有权
标题翻译：可互连的纳米级计算阶段
公开(公告)号：US07307448B2
公开(公告)日：2007-12-11
申请号：US11136935
申请日：2005-05-24
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/173
CPC分类号： H01L29/0665 , B82Y10/00 , H01L27/10 , H01L29/0673 , Y10S977/938
摘要： Embodiments of the present invention implement computing circuits comprising a number of interconnectable nanoscale computational stages. Each nanoscale computational stage includes: (1) a nanoscale logic array; and (2) a number of nanoscale latch arrays interconnected with the configurable logic array. Each nanoscale computational stage receives signals and passes the signals through the nanoscale logic array and to a nanoscale latch array. Signals output from the nanoscale latch array can be routed to another nanoscale computational stage or out of the computing circuit.
摘要翻译：本发明的实施例实现了包括多个可互连的纳米尺度计算阶段的计算电路。每个纳米尺度的计算阶段包括：（1）纳米尺度逻辑阵列; 和（2）与可配置逻辑阵列互连的多个纳米级闩锁阵列。每个纳米尺度的计算阶段接收信号并将信号传递通过纳米级逻辑阵列并传递到纳米尺度的锁存阵列。从纳米级锁存器阵列输出的信号可以被路由到另一个纳米尺度的计算阶段或者离开计算电路。

6. 发明授权

US07405462B2 FPGA architecture at conventional and submicron scales 有权
标题翻译：常规和亚微米尺度的FPGA架构
公开(公告)号：US07405462B2
公开(公告)日：2008-07-29
申请号：US11343304
申请日：2006-01-31
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , B82Y10/00 , B82Y30/00 , G11C8/10 , G11C13/0007 , G11C13/0014 , G11C2213/15 , G11C2213/34 , G11C2213/51 , G11C2213/77 , G11C2213/81 , H03K19/17728 , H03K19/1778
摘要： Reconfigurable logic devices and methods of programming the devices are disclosed. The logic device includes a look-up table (LUT) and at least one storage element configured for sampling LUT output signals. The LUT comprises a plurality of input signals, an array of programmable impedance devices operably coupled to the input signals, and the LUT output signals. Each programmable impedance device in the array includes a first electrode operably coupled to one of the input signal, a second electrode disposed to form a junction wherein the second electrode at least partially overlaps the first electrode, and a programmable material disposed between the first electrode and the second electrode. The programmable material operably couples the first electrode and the second electrode such that each programmable impedance device exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional or two-dimensional array.
摘要翻译：公开了可重构逻辑器件和编程器件的方法。逻辑器件包括查找表（LUT）和配置用于对LUT输出信号进行采样的至少一个存储元件。 LUT包括多个输入信号，可操作地耦合到输入信号的可编程阻抗装置的阵列和LUT输出信号。阵列中的每个可编程阻抗器件包括可操作地耦合到输入信号中的一个的第一电极，设置成形成其中第二电极至少部分地与第一电极重叠的结的第二电极和设置在第一电极和第二电极。可编程材料可操作地耦合第一电极和第二电极，使得每个可编程阻抗装置呈现非易失性可编程阻抗。该阵列可以被配置为一维或二维阵列。

7. 发明授权

US07242215B2 Nanoscale latches and impedance-encoded logic for use in nanoscale state machines, nanoscale pipelines, and in other nanoscale electronic circuits 有权
标题翻译：纳米尺度锁存器和阻抗编码逻辑，用于纳米级状态机，纳米级管道和其他纳米级电子电路
公开(公告)号：US07242215B2
公开(公告)日：2007-07-10
申请号：US10974660
申请日：2004-10-27
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： H03K19/173
CPC分类号： B82Y10/00 , G11C13/02 , G11C2213/77 , G11C2213/81 , H03K19/02 , Y10S977/789
摘要： Various embodiments of the present invention are directed to implementation and use of logic-state-storing, impedance-encoded nanoscale, impedance-encoded latches that store logic values as impedance states within nanoscale electronic circuits that employ impedance-driven logic. In certain of these embodiments, use of nanoscale, impedance-encoded latches together with nanoscale electronic circuits that employ impedance-driven logic avoids cumulative degradation of voltage margins along a cascaded series of logic circuits and provides for temporary storage of intermediate logic values, allowing for practical interconnection of nanowire-crossbar-implemented logic circuits through nanoscale, impedance-encoded latches to other nanowire-crossbar-implemented logic circuits in order to implement complex, nanoscale-logic-circuit pipelines, nanoscale-logic-circuit-based state machines, and other complex logic devices with various different interconnection topologies and corresponding functionalities.
摘要翻译：本发明的各种实施例涉及逻辑状态存储，阻抗编码的纳米级阻抗编码锁存器，其将逻辑值存储为采用阻抗驱动逻辑的纳米级电子电路内的阻抗状态。在这些实施例的某些实施例中，使用纳米级阻抗编码的锁存器以及采用阻抗驱动逻辑的纳米级电子电路避免沿着级联的逻辑电路系列的电压裕度的累积劣化，并且提供中间逻辑值的临时存储，允许将纳米线交叉开关逻辑电路通过纳米尺度阻抗编码的锁存器实际互连到其他纳米线交叉开关逻辑电路，以便实现复杂的纳米级逻辑电路管道，基于纳米级逻辑电路的状态机和具有各种不同互连拓扑和相应功能的其他复杂逻辑器件。

8. 发明授权

US5729752A Network connection scheme 失效
标题翻译：网络连接方案
公开(公告)号：US5729752A
公开(公告)日：1998-03-17
申请号：US19499
申请日：1993-02-19
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： G06F15/16 , G06F13/40 , G06F15/173 , H05K1/14 , G06F1/00
CPC分类号： H05K1/14 , G06F13/409 , G06F15/17343
摘要： A network connection scheme for a direct or an indirect network. The network is implemented in two levels of circuit boards. Every board in the first level crosses all the boards in the second level, with every processor in the first level circuit board coupled to at least two processors that are on two second level circuit boards. This scheme significantly reduces the difficulty in implementing the network.
摘要翻译：用于直接或间接网络的网络连接方案。网络实现在两层电路板上。第一级的每个电路板跨越第二级的所有电路板，第一级电路板中的每个处理器耦合到两个二级电路板上的至少两个处理器。该方案大大降低了实现网络的难度。

9. 发明授权

US08004876B2 Configurable molecular switch array 失效
标题翻译：可配置的分子开关阵列
公开(公告)号：US08004876B2
公开(公告)日：2011-08-23
申请号：US10233232
申请日：2002-08-30
申请人： Gregory S. Snider , Philip J. Kuekes , R. Stanley Williams
发明人： Gregory S. Snider , Philip J. Kuekes , R. Stanley Williams
IPC分类号： G11C11/00
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C2213/14 , G11C2213/34 , G11C2213/77 , G11C2213/81
摘要： A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.
摘要翻译：用于实现具有增益的至少一个电子电路的计算系统包括至少一个二维分子开关阵列。分子开关阵列通过将两个或更多个交叉的导线平面组装成器件的配置而形成。每个装置包括由一对交叉线形成的连接点和连接该连接处的一对交叉线的至少一个连接器种类。该结具有纳米的功能尺寸，并且包括由（1）一个或多个连接器种类和一对交叉导线提供的切换能力，以及（2）具有第一状态的可配置纳米级线晶体管，其具有作为晶体管和作为导电半导体线的第二状态。进行具体的连接来连接设备并将设备连接到提供高和低电压的两个结构。

10. 发明授权

US07525833B2 Nanoscale shift register and signal demultiplexing using microscale/nanoscale shift registers 有权
标题翻译：使用微米/纳米级移位寄存器的纳米级移位寄存器和信号解复用
公开(公告)号：US07525833B2
公开(公告)日：2009-04-28
申请号：US11255722
申请日：2005-10-21
申请人： Gregory S. Snider , Philip J. Kuekes
发明人： Gregory S. Snider , Philip J. Kuekes
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0023 , G11C19/00 , G11C2213/17 , G11C2213/77 , G11C2213/81
摘要： One embodiment of the present invention is a nanoscale shift register that can be used, in certain nanoscale and mixed-scale logic circuits, to distribute an input signal to individual nanowires of the logic circuit. In a described embodiment, the nanoscale shift register includes two series of nanoscale latches, each series controlled by common latch-control signals. Internal latches of each series of latches are alternatively interconnected with a previous latch of the other series and a next latch of the other series by two series of gates, each controlled by a gate signal line.
摘要翻译：本发明的一个实施例是纳米级移位寄存器，其可以在某些纳米尺度和混合尺度的逻辑电路中用于将输入信号分配到逻辑电路的各个纳米线。在所描述的实施例中，纳米尺度移位寄存器包括两个系列的纳米尺度锁存器，每个串联由公共锁存控制信号控制。每个锁存器系列的内部锁存器交替地与另一个串联的先前锁存器和另一个串联的下一个锁存器通过两个串联的栅极互连，每个栅极由栅极信号线控制。

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