专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140011367A1 Low Temperature Etching of Silicon Nitride Structures Using Phosphoric Acid Solutions 失效
标题翻译：使用磷酸溶液的氮化硅结构的低温蚀刻
公开(公告)号：US20140011367A1
公开(公告)日：2014-01-09
申请号：US13541397
申请日：2012-07-03
申请人： Gregory Nowling , John Foster
发明人： Gregory Nowling , John Foster
IPC分类号： H01L21/306
CPC分类号： H01L21/31111 , H01L21/67086 , H01L29/6653
摘要： Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.
摘要翻译：提供了用于处理半导体衬底的方法。该方法包括使用保持在低温（例如约110℃至130℃）之间的磷酸溶液来蚀刻氮化硅结构。这些温度提供足够的蚀刻速率，并且不会损坏周围的金属硅化物和氧化硅结构。氮化硅的蚀刻速率可以为每分钟10埃或更高。较低的温度也允许蚀刻溶液中磷酸的浓度降低，在一些实施方案中磷酸的浓度可以小于90重量％。结果，可以实现对氮化硅结构的更多的选择性蚀刻。相对于硅化物和氧化硅结构，该选择性可高达百倍。通过该蚀刻工艺，硅化物结构的表面电导率可以保持基本不变。

2. 发明授权

US08716146B2 Low temperature etching of silicon nitride structures using phosphoric acid solutions 失效
标题翻译：使用磷酸溶液对氮化硅结构进行低温蚀刻
公开(公告)号：US08716146B2
公开(公告)日：2014-05-06
申请号：US13541397
申请日：2012-07-03
申请人： Gregory Nowling , John Foster
发明人： Gregory Nowling , John Foster
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/67086 , H01L29/6653
摘要： Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110° C. and 130° C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.
摘要翻译：提供了用于处理半导体衬底的方法。该方法包括使用保持在低温（例如约110℃至130℃）之间的磷酸溶液来蚀刻氮化硅结构。这些温度提供足够的蚀刻速率，并且不会损坏周围的金属硅化物和氧化硅结构。氮化硅的蚀刻速率可以为每分钟10埃或更高。较低的温度也允许蚀刻溶液中磷酸的浓度降低，在一些实施方案中磷酸的浓度可以小于90重量％。结果，可以实现对氮化硅结构的更多的选择性蚀刻。相对于硅化物和氧化硅结构，该选择性可高达百倍。通过该蚀刻工艺，硅化物结构的表面电导率可以保持基本不变。

3. 发明申请

US20130203245A1 METHODS FOR PFET FABRICATION USING APM SOLUTIONS 有权
标题翻译：使用APM解决方案的PFET制造方法
公开(公告)号：US20130203245A1
公开(公告)日：2013-08-08
申请号：US13564071
申请日：2012-08-01
申请人： Joanna WASYLUK , Stephan KRONHOLZ , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
发明人： Joanna WASYLUK , Stephan KRONHOLZ , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
IPC分类号： H01L21/20
CPC分类号： H01L21/02057 , H01L21/30604 , H01L21/30608 , H01L21/76232 , H01L21/823807 , H01L21/823878
摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.
摘要翻译：一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。第一部分和第二部分由浅沟槽隔离特征电隔离。该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

4. 发明授权

US08703620B2 Methods for PFET fabrication using APM solutions 有权
标题翻译：使用APM解决方案的PFET制造方法
公开(公告)号：US08703620B2
公开(公告)日：2014-04-22
申请号：US13564071
申请日：2012-08-01
申请人： Joanna Wasyluk , Stephan Kronholz , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
发明人： Joanna Wasyluk , Stephan Kronholz , Berthold Reimer , Sven Metzger , Gregory Nowling , John Foster , Paul Besser
IPC分类号： H01L21/302
CPC分类号： H01L21/02057 , H01L21/30604 , H01L21/30608 , H01L21/76232 , H01L21/823807 , H01L21/823878
摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.
摘要翻译：一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。第一部分和第二部分通过浅沟槽隔离特征电隔离。该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

5. 发明申请

US20080014445A1 Chamberless Plasma Deposition of Coatings 审中-公开
标题翻译：无涂层等离子体沉积
公开(公告)号：US20080014445A1
公开(公告)日：2008-01-17
申请号：US11571238
申请日：2005-06-24
申请人： Robert Hicks , Gregory Nowling
发明人： Robert Hicks , Gregory Nowling
IPC分类号： B05D1/08 , B32B17/00 , C23C16/40 , C23C4/00 , C23C4/04 , C23C4/10 , H05H1/26
CPC分类号： C23C16/513 , C23C16/45595 , H05H1/46 , H05H2001/466 , H05H2001/4697 , Y10T428/31
摘要： A system and method of depositing coatings on a substrate includes providing a substrate in contact with air, and providing a plasma source (12) having a housing (16) surrounding a first electrode (18) and a second electrode (20) spaced from the first electrode. A plasma is generated by applying a signal to the first electrode and exciting a gas between the first electrode and the second electrode. A substantially uniform flux of at least one reactive specie is generated over an area larger than 1 cm2. The plasma is emitted into the air and toward the substrate. Various embodiments of the system and method allow high speed deposition of coatings on even thermally-sensitive substrates without the need of a chamber enclosing the substrate.
摘要翻译：在衬底上沉积涂层的系统和方法包括提供与空气接触的衬底，以及提供等离子体源（12），其具有围绕第一电极（18）的壳体（16）和与第一电极间隔开的第二电极（20）第一电极。通过向第一电极施加信号并激励第一电极和第二电极之间的气体来产生等离子体。在大于1cm 2的区域上产生至少一种反应物质的基本均匀的通量。等离子体被排放到空气中并朝向基板。该系统和方法的各种实施例允许在均匀的热敏基底上高速沉积涂层，而不需要包围基底的腔室。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式