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1. 发明授权

US07442595B2 Bipolar transistor with collector having an epitaxial Si:C region 失效
标题翻译：具有集电极的双极晶体管具有外延Si：C区域
公开(公告)号：US07442595B2
公开(公告)日：2008-10-28
申请号：US11511047
申请日：2006-08-28
申请人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D. Stricker
IPC分类号： H01L21/337
CPC分类号： H01L29/66068 , H01L29/2003 , H01L29/66242
摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.
摘要翻译：提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

2. 发明授权

US07170083B2 Bipolar transistor with collector having an epitaxial Si:C region 有权
标题翻译：具有集电极的双极晶体管具有外延Si：C区域
公开(公告)号：US07170083B2
公开(公告)日：2007-01-30
申请号：US10905510
申请日：2005-01-07
申请人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg , Andreas D Stricker
IPC分类号： H01L29/06
CPC分类号： H01L29/66068 , H01L29/2003 , H01L29/66242
摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.
摘要翻译：提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

3. 发明申请

US20080128861A1 METHODS TO IMPROVE THE SiGe HETEROJUNCTION BIPOLAR DEVICE PERFORMANCE 失效
标题翻译：改善SiGe异性双极性器件性能的方法
公开(公告)号：US20080128861A1
公开(公告)日：2008-06-05
申请号：US11555906
申请日：2006-11-02
申请人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L29/73
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.
摘要翻译：提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

4. 发明授权

US07476914B2 Methods to improve the SiGe heterojunction bipolar device performance 失效
标题翻译：改善SiGe异质结双极器件性能的方法
公开(公告)号：US07476914B2
公开(公告)日：2009-01-13
申请号：US11555906
申请日：2006-11-02
申请人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.
摘要翻译：提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

5. 发明授权

US07144787B2 Methods to improve the SiGe heterojunction bipolar device performance 有权
公开(公告)号：US07144787B2
公开(公告)日：2006-12-05
申请号：US10908363
申请日：2005-05-09
申请人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

6. 发明授权

US06858485B2 Method for creation of a very narrow emitter feature 失效
标题翻译：用于创建非常窄的发射器特征的方法
公开(公告)号：US06858485B2
公开(公告)日：2005-02-22
申请号：US10249780
申请日：2003-05-07
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L21/8238
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped emitter formed in the surface of the intrinsic base. Form an etch stop dielectric layer over the intrinsic base layer above the collector. Form a base contact layer of a conductive material over the etch stop dielectric layer and the intrinsic base layer. Form a second dielectric layer over the base contact layer. Etch a wide window through the dielectric layer and the base contact layer stopping the etching of the window at the etch stop dielectric layer. Form an island or a peninsula narrowing the wide window leaving at least one narrowed window within the wide window. Form sidewall spacers in the either the wide window or the narrowed window. Fill the windows with doped polysilicon to form an extrinsic emitter. Form an emitter below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面上的掺杂发射极。在收集器上方的本征基底层上形成蚀刻停止介电层。在蚀刻停止介电层和本征基极层上形成导电材料的基底接触层。在基底接触层上形成第二介电层。通过介电层和基底接触层蚀刻宽窗口，停止在蚀刻停止介电层处的窗口的蚀刻。形成一个岛屿或一个半岛，缩小广阔的窗户，在宽阔的窗口内至少留出一个狭窄的窗户。在宽窗口或狭窄的窗户中形成侧壁间隔物。用掺杂多晶硅填充窗口以形成外部发射极。在本征基表面的外部发射极之下形成发射体。

7. 发明授权

US07180157B2 Bipolar transistor with a very narrow emitter feature 失效
标题翻译：双极晶体管具有非常窄的发射极特性
公开(公告)号：US07180157B2
公开(公告)日：2007-02-20
申请号：US10978775
申请日：2004-11-01
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette , Andreas D. Stricker
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L29/0804 , H01L29/732
摘要： A double-polysilicon, self-aligned bipolar transistor has a collector region formed in a doped semiconductor substrate, an intrinsic counterdoped base formed on the surface of the substrate and a doped intrinsic emitter formed in the surface of the intrinsic base. An etch stop insulator layer overlies the intrinsic base layer above the collector. A base contact layer of a conductive material overlies the etch stop dielectric layer and the intrinsic base layer. A dielectric layer overlies the base contact layer. A wide window extends through the insulator layer and the base contact layer down to the insulator layer. An island or a peninsula is formed in the wide window leaving at least one narrowed window within the wide window, with sidewall spacers in either the wide window or the narrowed window. The narrowed windows are filled with doped polysilicon forming an extrinsic emitter with the intrinsic emitter formed below the extrinsic emitter in the surface of the intrinsic base.
摘要翻译：双重多晶硅，自对准双极晶体管具有在掺杂半导体衬底中形成的集电极区域，形成在衬底表面上的本征反掺杂基底和形成在本征基底表面的掺杂本征发射极。蚀刻停止绝缘体层覆盖在收集器上方的本征基极层。导电材料的基极接触层覆盖在蚀刻停止介电层和本征基极层之间。电介质层覆盖在基底接触层上。宽窗口延伸穿过绝缘体层和基底接触层向下延伸到绝缘体层。在宽窗口中形成岛或半岛，在宽窗口内留下至少一个变窄的窗口，在宽窗口或狭窄窗口中具有侧壁间隔物。变窄的窗口填充有掺杂的多晶硅，其形成外部发射极，本征发射极在本征基极表面的外部发射极之下形成。

8. 发明授权

US07119416B1 Bipolar transistor structure with self-aligned raised extrinsic base and methods 有权
公开(公告)号：US07119416B1
公开(公告)日：2006-10-10
申请号：US11169444
申请日：2005-06-29
申请人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
发明人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
IPC分类号： H01L27/82 , H01L29/70
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

9. 发明授权

US06982442B2 Structure and method for making heterojunction bipolar transistor having self-aligned silicon-germanium raised extrinsic base 失效
标题翻译：用于制造具有自对准硅 - 锗的异质结双极晶体管的结构和方法引起的外在基极
公开(公告)号：US06982442B2
公开(公告)日：2006-01-03
申请号：US10707712
申请日：2004-01-06
申请人： Kevin K. Chan , Marwan H. Khater , Kathryn T. Schonenberg , Panda Siddhartha
发明人： Kevin K. Chan , Marwan H. Khater , Kathryn T. Schonenberg , Panda Siddhartha
IPC分类号： H01L29/737
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： A heterojunction bipolar transistor (HBT) and method of making an HBT are provided. The HBT includes a collector, and an intrinsic base overlying the collector. The intrinsic base includes a layer of a single-crystal semiconductor alloy. The HBT further includes a raised extrinsic base having a first semiconductive layer overlying the intrinsic base and a second semiconductive layer formed on the first semiconductive layer. An emitter overlies the intrinsic base, and is disposed in an opening of the first and second semiconductive layers, such that the raised extrinsic base is self-aligned to the emitter.
摘要翻译：提供异质结双极晶体管（HBT）和制造HBT的方法。 HBT包括收集器和覆盖收集器的本征基极。本征基底包括一层单晶半导体合金。 HBT还包括凸起的非本征基底，其具有覆盖本征基底的第一半导体层和形成在第一半导体层上的第二半导体层。发射极覆盖本征基极，并且设置在第一和第二半导体层的开口中，使得凸出的外基极与发射极自对准。

10. 发明授权

US07037798B2 Bipolar transistor structure with self-aligned raised extrinsic base and methods 有权
标题翻译：双极晶体管结构具有自对准引出的外在基极和方法
公开(公告)号：US07037798B2
公开(公告)日：2006-05-02
申请号：US10904482
申请日：2004-11-12
申请人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
发明人： Thomas N. Adam , Kevin K. Chan , Alvin J. Joseph , Marwan H. Khater , Qizhi Liu , Beth Ann Rainey , Kathryn T. Schonenberg
IPC分类号： H01L21/331
CPC分类号： H01L29/7378 , H01L29/1004 , H01L29/66242 , H01L29/66287
摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.
摘要翻译：本发明包括制造双极晶体管的方法，该双极晶体管在形成连接层之前，将硅锗（SiGe）层或例如高压氧化物（HIPOX）的第三绝缘体层与邻近本征基极的发射极帽顶上相加。该添加允许使用湿蚀刻化学去除连接层，以去除在不使用氧化的情况下形成在发射极帽顶上的多余SiGe或第三绝缘体层。在这种情况下，可以使用氧化物部分（通过沉积氧化物或上述HIPOX层的分离）和氮化物间隔物形成发射极 - 基极隔离。本发明导致较低的热循环，较低的应力水平和对发射极盖层厚度的更多控制，这是第一实施例的缺点。本发明还包括所得到的双极晶体管结构。

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