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    • 7. 发明申请
    • Partially decoded register renamer
    • 部分解码寄存器重命名
    • US20070050602A1
    • 2007-03-01
    • US11214193
    • 2005-08-29
    • Wei-Han LienJohn YongShyam SundarRajat Goel
    • Wei-Han LienJohn YongShyam SundarRajat Goel
    • G06F9/30
    • G06F9/3836G06F9/384G06F9/3857G06F9/3861
    • In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that writes the respective renameable resource. Coupled to receive an input representing one or more retiring instruction identifiers corresponding to instruction operations that are being retired, the compare circuitry is configured to detect a match between at least a first identifier in a first storage location and one of the retiring identifiers. An encoded form of the identifiers is logically divided into a plurality of fields, and the input comprises a first plurality of bit vectors. Each of the first plurality of bit vectors corresponds to a respective field and includes a bit position for each possible value of the respective field.
    • 在一个实施例中,重新映射器包括多个存储位置和比较电路。 每个存储位置被分配给相应的可重命名资源,并且被配置为存储对应于写入相应可重命名资源的最小指令操作的标识符。 耦合以接收表示与正在退休的指令操作相对应的一个或多个退休指令标识符的输入,所述比较电路被配置为检测第一存储位置中的至少第一标识符与退出标识符之一的匹配。 标识符的编码形式在逻辑上被划分为多个字段,并且输入包括第一多个比特向量。 第一多个位向量中的每一个对应于相应的场,并且包括相应场的每个可能值的比特位置。
    • 10. 发明申请
    • Address Generation Unit with Pseudo Sum to Accelerate Load/Store Operations
    • 地址生成单位,具有伪和,加速加载/存储操作
    • US20110022824A1
    • 2011-01-27
    • US12506311
    • 2009-07-21
    • Rajat GoelChen-Ju Hsieh
    • Rajat GoelChen-Ju Hsieh
    • G06F9/30
    • G06F9/3017G06F7/506G06F7/60G06F9/355G06F9/3824
    • In an embodiment, an address generation unit (AGU) is configured to generate a pseudo sum from an index portion of two or more operands. The pseudo sum may equal the index if the carry-in of the actual sum to the least significant bit of the index is a selected value (e.g. zero). The AGU may also include circuitry coupled to receive the operands and to generate the actual carry-in to the least significant bit of the index. The AGU may transmit the pseudo sum and the carry-in to a decode block for a memory array. The decode block may decode the pseudo sum into one or more one-hot vectors. The one-hot vectors may be input to muxes, and the one-hot vectors rotated by one position may be the other input. The actual carry-in may be the selection control of the mux.
    • 在一个实施例中,地址生成单元(AGU)被配置为从两个或更多个操作数的索引部分生成伪和。 如果实际和到索引的最低有效位的进位是一个选定的值(例如零),那么伪和可以等于索引。 AGU还可以包括耦合以接收操作数并且生成索引的最低有效位的实际载入的电路。 AGU可以将伪和和携带发送到用于存储器阵列的解码块。 解码块可以将伪和解码成一个或多个单向量向量。 单热矢量可以被输入到多路复用器,并且旋转一个位置的一个热向量可以是另一个输入。 实际的进位可能是多路复用器的选择控制。