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1. 发明授权

US07549156B2 Fast channel scanning and acquisition system and method for cable modem applications 有权
标题翻译：电缆调制解调器应用的快速通道扫描和采集系统和方法
公开(公告)号：US07549156B2
公开(公告)日：2009-06-16
申请号：US10677110
申请日：2003-10-01
申请人： Gordon Y. Li , Yoav Hebron , Bruce A. Grove , Adrian Kwong
发明人： Gordon Y. Li , Yoav Hebron , Bruce A. Grove , Adrian Kwong
IPC分类号： H04N7/173
CPC分类号： H04N21/42676 , H04N7/17309 , H04N21/4383
摘要： A programmable channel scanning and acquisition method for a cable modem first performs a fast scan and then a slow scan to identify channels supporting cable modem services. The fast scan involves only a check of the cable modem AGC lock. A list of potentially operational channels is assembled and scanned. The list includes, in order of preference, the last known good channel, golden channels that are likely to support cable modem services, “learned” golden channels consisting of previous last known good channels, and other channels within the frequency plan range. The list omits channels on a “black list” known not to be operational and channels outside of the frequency range, except during registration. The method may be optimized by the setting of various parameters for operation in a DOCSIS or EuroDOCSIS environment.
摘要翻译：用于电缆调制解调器的可编程通道扫描和采集方法首先执行快速扫描，然后执行慢速扫描以识别支持有线调制解调器服务的信道。快速扫描仅涉及电缆调制解调器AGC锁的检查。组合和扫描潜在的操作通道的列表。该列表按照优先顺序包括最后一个已知的良好频道，可能支持有线调制解调器服务的黄金频道，“学习”由前一个已知的好频道组成的黄金频道以及频率计划范围内的其他频道。除了注册之外，该列表省略了已知无法运行的“黑名单”和频率范围以外的频道的频道。该方法可以通过设置DOCSIS或EuroDOCSIS环境中的各种参数进行优化。

2. 发明授权

US08223775B2 Architecture for a flexible and high-performance gateway cable modem 有权
标题翻译：灵活高性能网关电缆调制解调器的架构
公开(公告)号：US08223775B2
公开(公告)日：2012-07-17
申请号：US10675566
申请日：2003-09-30
申请人： Gordon Y. Li , Yoav Hebron
发明人： Gordon Y. Li , Yoav Hebron
IPC分类号： H04L12/46
CPC分类号： H04L12/2803 , H04L12/2834
摘要： A cable modem system and architecture. A cable modem engine performs all cable modem functions, and a data networking engine performs all data and home networking functions. The cable modem engine is completely partitioned from the data networking engine. DOCSIS and VoIP functionality is implemented in the cable modem engine. The VoIP functionality may be in accordance with the PacketCable specification. The data networking functionality provided by the data networking engine may be in accordance with the CableHome specification.
摘要翻译：电缆调制解调器系统和架构。电缆调制解调器引擎执行所有电缆调制解调器功能，数据网络引擎执行所有数据和家庭网络功能。电缆调制解调器引擎与数据网络引擎完全分离。 DOCSIS和VoIP功能在电缆调制解调器引擎中实现。 VoIP功能可能符合PacketCable规范。数据网络引擎提供的数据联网功能可能符合CableHome规范。

3. 发明申请

US20050076385A1 Fast channel scanning and acquisition system and method for cable modem applications 有权
标题翻译：电缆调制解调器应用的快速通道扫描和采集系统和方法
公开(公告)号：US20050076385A1
公开(公告)日：2005-04-07
申请号：US10677110
申请日：2003-10-01
申请人： Gordon Li , Yoav Hebron , Bruce Grove , Adrian Kwong
发明人： Gordon Li , Yoav Hebron , Bruce Grove , Adrian Kwong
IPC分类号： H04N7/173
CPC分类号： H04N21/42676 , H04N7/17309 , H04N21/4383
摘要： A programmable channel scanning and acquisition method for a cable modem first performs a fast scan and then a slow scan to identify channels supporting cable modem services. The fast scan involves only a check of the cable modem AGC lock. A list of potentially operational channels is assembled and scanned. The list includes, in order of preference, the last known good channel, golden channels that are likely to support cable modem services, “learned” golden channels consisting of previous last known good channels, and other channels within the frequency plan range. The list omits channels on a “black list” known not to be operational and channels outside of the frequency range, except during registration. The method may be optimized by the setting of various parameters for operation in a DOCSIS or EuroDOCSIS environment.
摘要翻译：用于电缆调制解调器的可编程通道扫描和采集方法首先执行快速扫描，然后执行慢速扫描以识别支持有线调制解调器服务的信道。快速扫描仅涉及电缆调制解调器AGC锁的检查。组合和扫描潜在的操作通道的列表。该列表按照优先顺序包括最后一个已知的良好频道，可能支持有线调制解调器服务的黄金频道，“学习”由前一个已知的好频道组成的黄金频道以及频率计划范围内的其他频道。除了注册之外，该列表省略了已知无法运行的“黑名单”和频率范围以外的频道的频道。该方法可以通过设置DOCSIS或EuroDOCSIS环境中的各种参数进行优化。

4. 发明授权

US5272661A Finite field parallel multiplier 失效
标题翻译：有限域并行乘法器
公开(公告)号：US5272661A
公开(公告)日：1993-12-21
申请号：US990524
申请日：1992-12-15
申请人： Sreenivasa A. Raghavan , Yoav Hebron , Itzhak Gurantz , James N. Esserman
发明人： Sreenivasa A. Raghavan , Yoav Hebron , Itzhak Gurantz , James N. Esserman
IPC分类号： G06F7/72 , G06F7/00
CPC分类号： G06F7/724
摘要： A finite field parallel multiplier in GF(q.sup.m) including a router for directing 2m-1 components in m groups of m single-component signal lines towards m computing circuits for performing multiply and add modulo-q. The router guides m components from a first finite field element along with an additional m-1 components generated from linear combinations of the m components of the first finite field element. Each of the computing circuits receives all of the components from the second finite field element and m components provided by one set of signal lines through the router. Each computing circuit generates a single component for the resultant finite field element. These resulting components may be input through a basis change circuit to obtain a result in the desired basis.
摘要翻译： GF（qm）中的有限域并行乘法器包括路由器，用于将m个单分量信号线的m组中的2m-1分量指向m个运算电路，用于执行乘法和加法模q。路由器引导来自第一有限域元素的分量以及从第一有限域元素的m个分量的线性组合生成的附加m-1分量。每个计算电路接收来自第二有限域元素的所有分量，以及通过路由器由一组信号线提供的m个分量。每个计算电路为所得到的有限域元素生成单个分量。可以通过基础改变电路输入这些所得到的组件，以获得期望的结果。

5. 发明授权

US6101228A Receiver of wideband digital signal in the presence of a narrow band interfering signal 失效
公开(公告)号：US6101228A
公开(公告)日：2000-08-08
申请号：US861669
申请日：1997-05-22
申请人： Yoav Hebron , Sree A. Raghavan , Itzhak Gurantz
发明人： Yoav Hebron , Sree A. Raghavan , Itzhak Gurantz
IPC分类号： H04B1/10 , H04B1/71 , H04L25/03 , H03D1/04
CPC分类号： H04B1/7101 , H04B1/1036 , H04L25/03038 , H04L2025/0342 , H04L2025/03471
摘要： A desired signal having a wide frequency band and including sequential symbols representing digital values is discriminated from a narrow band interfering signal having a carrier frequency in the wide band by initially applying both signals to a filter so both signals are passed to an output of the filter. In response to the filter output, estimates of the values of received symbols of the desired signal are derived and compared to the filter output to derive an error representing signal. A characteristic of the filter is controlled in response to the error representing signal so the filter is adjusted to reject the interfering signal and pass the desired signal.

6. 发明授权

US08861357B2 Method and apparatus for communicating unicast PQoS DFID information 有权
标题翻译：用于传播单播PQoS DFID信息的方法和装置
公开(公告)号：US08861357B2
公开(公告)日：2014-10-14
申请号：US12955642
申请日：2010-11-29
申请人： Yoav Hebron
发明人： Yoav Hebron
IPC分类号： H04L12/28 , H04L12/911
CPC分类号： H04L12/2801 , H04L47/781
摘要： Methods and apparatus for communicating unicast PQoS DFID information in a MoCA network are disclosed. In a transmitting apparatus, values are assigned in a first set of fields of a reservation request element, the first set adapted to indicate a unicast PQoS flow with a DFID value. Values are assigned in a second set of fields of the reservation request element, the second set adapted to represent the DFID value. A message comprising the reservation request element is transmitted to a network coordinator. In a receiving network coordinator, a message comprising a reservation request element is received, the reservation request element comprising a first set of fields and a second set of fields. It is determined whether the first set is indicative of a unicast PQoS flow with a DFID value. The DFID value is determined from the second set if the first set is indicative of a unicast PQoS flow with a DFID value.
摘要翻译：公开了在MoCA网络中传送单播PQoS DFID信息的方法和装置。在发送装置中，在预约请求单元的第一组字段中分配值，该第一组适于指示具有DFID值的单播PQoS流。值在预约请求单元的第二组字段中分配，第二组适于表示DFID值。包括预留请求单元的消息被发送到网络协调器。在接收网络协调器中，接收到包括预留请求单元的消息，所述预留请求单元包括第一组字段和第二组字段。确定第一组是否指示具有DFID值的单播PQoS流。如果第一组指示具有DFID值的单播PQoS流，则从第二组确定DFID值。

7. 发明授权

US08522061B2 Method and apparatus of power management of a node in home entertainment network by shifting from a normal state into either a first low power state based on the traffic at the node or a second low power state upon receipt of a message granting a request for the second low power state at the node 有权
标题翻译：家庭娱乐网络中的节点的功率管理方法和装置，通过在接收到授予第二个请求的消息的消息时，基于节点处的业务或第二低功率状态从正常状态转换到第一低功率状态节点处的低功率状态
公开(公告)号：US08522061B2
公开(公告)日：2013-08-27
申请号：US12717384
申请日：2010-03-04
申请人： Yoav Hebron , Michail Tsatsanis , Changwen Liu , Na Chen
发明人： Yoav Hebron , Michail Tsatsanis , Changwen Liu , Na Chen
IPC分类号： G06F1/00 , G08C17/00
CPC分类号： G06F1/3209 , H04L12/10
摘要： A power management system for home entertainment networks having three power states. The network controller is empowered to move nodes within the home entertainment network between the power states.
摘要翻译：一种具有三种电源状态的家庭娱乐网络的电源管理系统。网络控制器被授权在家庭娱乐网络之间在电力状态之间移动节点。

8. 发明申请

US20050071492A1 Architecture for a flexible and high-performance gateway cable modem 有权
标题翻译：灵活高性能网关电缆调制解调器的架构
公开(公告)号：US20050071492A1
公开(公告)日：2005-03-31
申请号：US10675566
申请日：2003-09-30
申请人： Gordon Li , Yoav Hebron
发明人： Gordon Li , Yoav Hebron
IPC分类号： G06F15/16 , H04L12/28
CPC分类号： H04L12/2803 , H04L12/2834
摘要： A cable modem system and architecture. A cable modem engine performs all cable modem functions, and a data networking engine performs all data and home networking functions. The cable modem engine is completely partitioned from the data networking engine. DOCSIS and VoIP functionality is implemented in the cable modem engine. The VoIP functionality may be in accordance with the PacketCable specification. The data networking functionality provided by the data networking engine may be in accordance with the CableHome specification.
摘要翻译：电缆调制解调器系统和架构。电缆调制解调器引擎执行所有电缆调制解调器功能，数据网络引擎执行所有数据和家庭网络功能。电缆调制解调器引擎与数据网络引擎完全分离。 DOCSIS和VoIP功能在电缆调制解调器引擎中实现。 VoIP功能可能符合PacketCable规范。数据网络引擎提供的数据联网功能可能符合CableHome规范。

9. 发明授权

US5319649A Transmission systems and decoders therefor 失效
标题翻译：传输系统和解码器
公开(公告)号：US5319649A
公开(公告)日：1994-06-07
申请号：US814889
申请日：1991-12-27
申请人： Sreenivasa A. Raghavan , Yoav Hebron
发明人： Sreenivasa A. Raghavan , Yoav Hebron
IPC分类号： H03M13/13 , H03M13/23 , H03M13/45 , G06F11/10 , H03M13/00 , H03M13/12
CPC分类号： H03M13/13 , H03M13/23 , H03M13/451 , H03M13/6577
摘要： Digital data is processed by quantizing the data to produce samples, each with a most significant bits and least significant bits with the least significant bits representing reliabilities, generating a parities from the most significant bits of the samples, generating weight functions corresponding to the parities on the basis of the number of times a reliability measure occurs, and producing a corrected stream of data with the weight functions and the corresponding parities.
摘要翻译：通过量化数据来产生数字以产生样本来处理数字数据，每个采样具有最高有效位和最低有效位，最低有效位表示可靠性，从采样的最高有效位产生奇偶校验，产生对应于奇偶校验的权重函数发生可靠性测量次数的基础，以及使用权重函数和相应的奇偶校验产生校正的数据流。

10. 发明授权

US5379243A Method and apparatus for performing finite field division 失效
标题翻译：执行有限场划分的方法和装置
公开(公告)号：US5379243A
公开(公告)日：1995-01-03
申请号：US938109
申请日：1992-08-31
申请人： Haim Greenberger , Yoav Hebron , Sreenivasa A. Raghavan
发明人： Haim Greenberger , Yoav Hebron , Sreenivasa A. Raghavan
IPC分类号： G06F7/72 , G06F7/52
CPC分类号： G06F7/726
摘要： An apparatus and method are provided for simplifying a finite field division, including inputs for the initial condition signals a(x), b(x), and p(x), and providing at an output node the signal c(x), where c(x)=a(x)/b(x) without intermediate inverter circuitry for finding 1/b(x). A reference register initialized to b(x), and a divider register initialized to a(x). Both registers are manipulated in parallel by a logic circuit which responds to the contents of the reference register, converting its contents to 1.Claim By applying the same manipulations to the divider register, its contents are converted from a(x) to a(x)/b(x).One embodiment of a finite field divider according to the present invention is used to provide a single finite field division of a single set of values a(x), b(x) and p(x). Another embodiment processes continuous streams of a(x), b(x) and p(x) values, to provide a continuous stream of c(x) values delayed by a calculation time. In yet another embodiment, p(x) is not a stream of values, but a constant either applied to the p(x) input of the finite field divider circuit or a constant defined by fixed circuit elements within the divider circuit.
摘要翻译：提供了一种用于简化有限域划分的装置和方法，包括用于初始条件信号a（x），b（x）和p（x）的输入，以及在输出节点处提供信号c（x），其中 c（x）= a（x）/ b（x），没有用于找到1 / b（x）的中间逆变器电路。初始化为b（x）的参考寄存器和初始化为（x）的分频器寄存器。两个寄存器由逻辑电路并行操作，逻辑电路响应参考寄存器的内容，将其内容转换为1.Claim通过对分频器寄存器应用相同的操作，其内容从（x）转换为（x））/ b（x）。根据本发明的有限场分割器的一个实施例用于提供单组值a（x），b（x）和p（x）的单个有限场划分。另一个实施例处理（x），b（x）和p（x）值的连续流，以提供延迟计算时间的c（x）值的连续流。在另一个实施例中，p（x）不是值流，而是施加到有限场分频器电路的p（x）输入或由分频器电路内的固定电路元件限定的常数的常数。

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