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1. 发明申请

US20160172236A1 DEVICE SUBSTRATES, INTEGRATED CIRCUITS AND METHODS FOR FABRICATING DEVICE SUBSTRATES AND INTEGRATED CIRCUITS 审中-公开
标题翻译：设备基板，集成电路和用于制造器件基板和集成电路的方法
公开(公告)号：US20160172236A1
公开(公告)日：2016-06-16
申请号：US14568294
申请日：2014-12-12
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Lian Hoon Ko , Yung Fu Chong
IPC分类号： H01L21/762 , H01L27/10 , H01L29/06
CPC分类号： H01L21/76229 , H01L21/823481 , H01L27/088
摘要： Integrated circuits and methods for fabricating device substrates and integrated circuits are provided. Integrated circuits in accordance with those described herein include a semiconductor substrate with a substrate surface and having a low voltage (LV) region and a second voltage region that is either a medium voltage (MV) region or a high voltage (HV) region. The integrated circuits also have semiconductor devices thereon with isolation trenches in between them. The corners of the trenches in MV and HV regions of the integrated circuit are more rounded than the corners of the trenches in the LV region so that interference by trench corners in the MV and HV regions with the operation and performance of adjacent MV or HV device is minimized. Methods for fabricating such integrated circuits, as well as device substrates from which such integrated circuits may be fabricated, involve providing a semiconductor substrate and overlaying various oxide layers thereon, along with performing nitride pullback techniques, and forming isolation trenches by shallow trench isolation techniques to form trench corners in MV and HV regions that are more rounded than trench corners in the LV region.
摘要翻译：提供了用于制造器件基板和集成电路的集成电路和方法。根据本文所述的集成电路包括具有衬底表面并且具有低电压（LV）区域和作为中压（MV）区域或高压（HV）区域）的第二电压区域的半导体衬底。集成电路还具有其上具有隔离沟槽的半导体器件。集成电路的MV和HV区域的沟槽的角部比LV区域中的沟槽的角部更圆，使得具有相邻MV或HV装置的操作和性能的MV和HV区域中的沟槽角的干扰被最小化。制造这样的集成电路的方法以及可以从其制造这样的集成电路的器件基板涉及提供半导体衬底并且覆盖其上的各种氧化物层以及执行氮化物回退技术，并且通过浅沟槽隔离技术形成隔离沟槽在MV区域和HV区域中形成比在LV区域中的沟槽角更圆的沟槽角。

2. 发明公开

US20240006517A1 TRANSISTOR WITH WRAP-AROUND EXTRINSIC BASE 审中-公开
公开(公告)号：US20240006517A1
公开(公告)日：2024-01-04
申请号：US18370001
申请日：2023-09-19
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Xinshu Cai , Shyue Seng Tan , Vibhor Jain , John J. Pekarik , Kien Seen Daniel Chong , Yung Fu Chong , Judson R. Holt , Qizhi Liu , Kenneth J. Stein
IPC分类号： H01L29/737 , H01L29/66 , H01L29/45 , H01L29/10
CPC分类号： H01L29/7371 , H01L29/66242 , H01L29/45 , H01L29/1004
摘要： The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

3. 发明申请

US20230127768A1 TRANSISTOR WITH WRAP-AROUND EXTRINSIC BASE 有权
公开(公告)号：US20230127768A1
公开(公告)日：2023-04-27
申请号：US17509604
申请日：2021-10-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Xinshu Cai , Shyue Seng Tan , Vibhor Jain , John J. Pekarik , Kien Seen Daniel Chong , Yung Fu Chong , Judson R. Holt , Qizhi Liu , Kenneth J. Stein
IPC分类号： H01L29/737 , H01L29/10 , H01L29/45 , H01L29/66
摘要： The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

4. 发明授权

US11855196B2 Transistor with wrap-around extrinsic base 有权
公开(公告)号：US11855196B2
公开(公告)日：2023-12-26
申请号：US17509611
申请日：2021-10-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Xinshu Cai , Shyue Seng Tan , Vibhor Jain , John J. Pekarik , Kien Seen Daniel Chong , Yung Fu Chong , Judson R. Holt , Qizhi Liu , Kenneth J. Stein
IPC分类号： H01L29/737 , H01L29/66 , H01L29/45 , H01L29/10
CPC分类号： H01L29/7371 , H01L29/1004 , H01L29/45 , H01L29/66242
摘要： The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

5. 发明授权

US10566441B2 Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures 有权
公开(公告)号：US10566441B2
公开(公告)日：2020-02-18
申请号：US15896696
申请日：2018-02-14
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Hao Nong , Liang Li , Chiew Wah Yap , Ting Huo , Yung Fu Chong , Yun Ling Tan
IPC分类号： H01L21/28 , H01L21/308 , H01L21/311 , H01L21/673 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/66
摘要： Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

6. 发明申请

US20230129914A1 TRANSISTOR WITH WRAP-AROUND EXTRINSIC BASE 有权
公开(公告)号：US20230129914A1
公开(公告)日：2023-04-27
申请号：US17509611
申请日：2021-10-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Xinshu Cai , Shyue Seng Tan , Vibhor Jain , John J. Pekarik , Kien Seen Daniel Chong , Yung Fu Chong , Judson R. Holt , Qizhi Liu , Kenneth J. Stein
IPC分类号： H01L29/737 , H01L29/10 , H01L29/45 , H01L29/66
摘要： The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

7. 发明授权

US10395987B2 Transistor with source-drain silicide pullback 有权
公开(公告)号：US10395987B2
公开(公告)日：2019-08-27
申请号：US15402150
申请日：2017-01-09
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Chia Ching Yeo , Kiok Boone Elgin Quek , Khee Yong Lim , Jae Han Cha , Yung Fu Chong
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/78
摘要： The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.

8. 发明申请

US20190252515A1 METHODS OF FORMING INTEGRATED CIRCUITS WITH SOLUTIONS TO INTERLAYER DIELECTRIC VOID FORMATION BETWEEN GATE STRUCTURES 审中-公开
公开(公告)号：US20190252515A1
公开(公告)日：2019-08-15
申请号：US15896696
申请日：2018-02-14
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Hao Nong , Liang Li , Chiew Wah Yap , Ting Huo , Yung Fu Chong , Yun Ling Tan
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/311 , H01L27/088
摘要： Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

9. 发明授权

US11855195B2 Transistor with wrap-around extrinsic base 有权
公开(公告)号：US11855195B2
公开(公告)日：2023-12-26
申请号：US17509604
申请日：2021-10-25
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Xinshu Cai , Shyue Seng Tan , Vibhor Jain , John J. Pekarik , Kien Seen Daniel Chong , Yung Fu Chong , Judson R. Holt , Qizhi Liu , Kenneth J. Stein
IPC分类号： H01L29/737 , H01L29/66 , H01L29/45 , H01L29/10
CPC分类号： H01L29/7371 , H01L29/1004 , H01L29/45 , H01L29/66242
摘要： The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.

10. 发明公开

US20230411208A1 AIR GAP WITH INVERTED T-SHAPED LOWER PORTION EXTENDING THROUGH AT LEAST ONE METAL LAYER, AND RELATED METHOD 审中-公开
公开(公告)号：US20230411208A1
公开(公告)日：2023-12-21
申请号：US17807905
申请日：2022-06-21
申请人： GlobalFoundries Singapore Pte. Ltd.
发明人： Wensheng Deng , Kemao Lin , Curtis Chun-I Hsieh , Wanbing Yi , Liu Xinfu , Rui Tze Toh , Yanxia Shao , Shucheng Yin , Jason Kin Wei Wong , Yung Fu Chong
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/7682 , H01L23/5226 , H01L21/76829 , H01L23/53295
摘要： Methods of forming semiconductor devices including an air gap extending through at least one metal layer, and the semiconductor device so formed, are disclosed. The air gap has a lower portion that contacts a silicide layer over a gate body of a transistor gate and has an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.

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