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1. 发明申请

US20150311221A1 INTEGRATED CIRCUITS HAVING NICKEL SILICIDE CONTACTS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有镍硅氧烷接触的集成电路及其制造方法
公开(公告)号：US20150311221A1
公开(公告)日：2015-10-29
申请号：US14259460
申请日：2014-04-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Jingyan Huang , Chuan Wang , Chim Seng Seet , Yun Ling Tan , Alex See
IPC分类号： H01L27/115 , H01L29/49 , H01L29/45 , H01L21/283 , H01L21/28
CPC分类号： H01L29/49 , H01L21/28273 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L27/11521 , H01L29/42328 , H01L29/456 , H01L29/665 , H01L29/66825
摘要： Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.
摘要翻译：提供了具有硅化镍触点的集成电路和用于制造具有硅化镍触点的集成电路的方法。用于制造集成电路的示例性方法包括提供半导体衬底并在半导体衬底上形成非易失性存储器结构。非易失性存储器结构包括栅极表面。该方法还包括在栅极表面上沉积含镍材料。此外，该方法包括对非易失性存储器结构进行退火并在含镍材料的栅极表面上形成硅化镍接触。

2. 发明授权

US10784332B2 Methods for producing integrated circuits with magnets and a wet etchant for the same 有权
公开(公告)号：US10784332B2
公开(公告)日：2020-09-22
申请号：US15928239
申请日：2018-03-22
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Liang Li , Yun Ling Tan , Kai Hung Alex See , Lulu Peng , Donald Ray Disney
IPC分类号： H01L49/02 , H01F41/02 , C09K13/08 , C23F1/26 , C23F1/30 , H01F41/04
摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.

3. 发明授权

US10410854B2 Method and device for reducing contamination for reliable bond pads 有权
公开(公告)号：US10410854B2
公开(公告)日：2019-09-10
申请号：US15857546
申请日：2017-12-28
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Honghui Mou , Xiaodong Li , Yun Ling Tan , Alex See , Liang Li
IPC分类号： H01L21/02 , H01L21/60
摘要： The present disclosure generally relates to methods for cleaning the backside of a wafer. A wet cleaning method may be used by stripping off the uppermost spacer layers on the backside of the wafer using a cleaning solution. In one embodiment, hydrogen fluoride (HF) solution may be employed to remove the nitride/oxide spacer layer. In another embodiment, a dry cleaning method may be employed to etch the wafer at the bevel region. Residues are completely removed from the wafer backside. This method improves the yield and storage life of the semiconductor wafers.

4. 发明授权

US10115625B2 Methods for removal of hard mask 有权
公开(公告)号：US10115625B2
公开(公告)日：2018-10-30
申请号：US15394851
申请日：2016-12-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Liang Li , Yun Ling Tan , Hai Cong , Changwei Pei , Alex See
IPC分类号： H01L21/762 , H01L21/306 , H01L21/308 , H01L21/3065 , H01L27/11548 , H01L27/11575
摘要： Embodiments of a method of processing semiconductor devices are presented. The method includes providing a substrate prepared with isolation regions having a non-planar surface topology. The substrate includes at least first and second regions. The first region includes a memory region and the second region includes a logic region. A hard mask layer is formed covering the substrate and the isolation regions with non-planar surface topology. The method includes selectively processing an exposed portion of the hard mask layer over a select region while protecting a portion of the hard mask layer over a non-select region. The top substrate area and isolation regions of the non-select region are not exposed during processing of the portion of the hard mask layer over the select region. Hard mask residue is completely removed over the select region during processing of the exposed portion of the hard mask layer.

5. 发明授权

US09548371B2 Integrated circuits having nickel silicide contacts and methods for fabricating the same 有权
标题翻译：具有硅化镍触点的集成电路及其制造方法
公开(公告)号：US09548371B2
公开(公告)日：2017-01-17
申请号：US14259460
申请日：2014-04-23
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Jingyan Huang , Chuan Wang , Chim Seng Seet , Yun Ling Tan , Alex See
IPC分类号： H01L21/336 , H01L29/49 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115 , H01L21/285 , H01L21/768 , H01L29/45
CPC分类号： H01L29/49 , H01L21/28273 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L27/11521 , H01L29/42328 , H01L29/456 , H01L29/665 , H01L29/66825
摘要： Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.
摘要翻译：提供了具有硅化镍触点的集成电路和用于制造具有硅化镍触点的集成电路的方法。用于制造集成电路的示例性方法包括提供半导体衬底并在半导体衬底上形成非易失性存储器结构。非易失性存储器结构包括栅极表面。该方法还包括在栅极表面上沉积含镍材料。此外，该方法包括对非易失性存储器结构进行退火并在含镍材料的栅极表面上形成硅化镍接触。

6. 发明授权

US09230886B2 Method for forming through silicon via with wafer backside protection 有权
公开(公告)号：US09230886B2
公开(公告)日：2016-01-05
申请号：US14575639
申请日：2014-12-18
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Lup San Leong , Zheng Zou , Alex Kai Hung See , Hai Cong , Xuesong Rao , Yun Ling Tan , Huang Liu
IPC分类号： H01L23/48 , H01L23/00 , H01L21/768 , H01L21/02 , H01L21/48
CPC分类号： H01L23/481 , H01L21/02107 , H01L21/486 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/13009 , H01L2224/1357
摘要： Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

7. 发明授权

US11315876B2 Thin film conductive material with conductive etch stop layer 有权
公开(公告)号：US11315876B2
公开(公告)日：2022-04-26
申请号：US16792854
申请日：2020-02-17
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Xuesong Rao , Yun Ling Tan , Yudi Setiawan , Siow Lee Chwa
IPC分类号： H01L23/535 , H01L23/532 , H01L21/768
摘要： A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad.

8. 发明授权

US10566441B2 Methods of forming integrated circuits with solutions to interlayer dielectric void formation between gate structures 有权
公开(公告)号：US10566441B2
公开(公告)日：2020-02-18
申请号：US15896696
申请日：2018-02-14
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Hao Nong , Liang Li , Chiew Wah Yap , Ting Huo , Yung Fu Chong , Yun Ling Tan
IPC分类号： H01L21/28 , H01L21/308 , H01L21/311 , H01L21/673 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/66
摘要： Methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of gate structures that have sidewalls spacers disposed adjacent to the gate structures. A gap is defined between sidewall spacers of adjacent gate structures. The method proceeds with decreasing an aspect ratio between a width of the gap at an opening thereto and a depth of the gap, wherein an aspect ratio between a width of the gap at a base of the sidewall spacers and the depth of the gap remains substantially unchanged after decreasing the aspect ratio between the width of the gap at the opening thereto.

9. 发明申请

US20190296100A1 METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH MAGNETS AND A WET ETCHANT FOR THE SAME 审中-公开
公开(公告)号：US20190296100A1
公开(公告)日：2019-09-26
申请号：US15928239
申请日：2018-03-22
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Liang Li , Yun Ling Tan , Kai Hung Alex See , Lulu Peng , Donald Ray Disney
IPC分类号： H01L49/02 , H01F41/02 , H01F41/04 , C23F1/26 , C23F1/30 , C09K13/08
摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower conductor element overlying a substrate, and forming a magnetic stack layer overlying the lower conductor element. A waste portion of the magnetic stack layer is removed with a wet etchant to produce a magnetic core. The wet etchant includes hydrofluoric acid, a second acid different than the hydrofluoric acid, an oxidizer, and a solvent.

10. 发明授权

US08860142B2 Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction 有权
标题翻译：使用热邻近校正来减少集成电路管芯内的热变化的方法和装置
公开(公告)号：US08860142B2
公开(公告)日：2014-10-14
申请号：US13648905
申请日：2012-10-10
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Debora Chyiu Hyia Poon , Alex K H See , Francis Benistant , Benjamin Colombeau , Yun Ling Tan , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/70 , H01L27/088 , H01L27/02
CPC分类号： H01L27/088 , H01L27/0211
摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
摘要翻译：制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。如果估计温度低于或高于预定目标温度（或范围），则执行TPC。可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化在退火期间。

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