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1. 发明授权

US5703826A Video random access memory chip configured to transfer data in response to an internal write signal 失效
标题翻译：配置为响应于内部写入信号传送数据的视频随机存取存储器芯片
公开(公告)号：US5703826A
公开(公告)日：1997-12-30
申请号：US619285
申请日：1996-03-18
申请人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
发明人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1033 , G11C7/1075
摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. Using the circuit of the invention data is transferred in response to an internal write signal. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
摘要翻译：本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可将数据的半字节写入VRAM 。使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。使用本发明的电路响应于内部写入信号传送数据。本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。

2. 发明授权

US5506814A Video random access memory device and method implementing independent two WE nibble control 失效
标题翻译：视频随机存取存储器件和方法实现独立的两个WE半字节控制
公开(公告)号：US5506814A
公开(公告)日：1996-04-09
申请号：US69967
申请日：1993-05-28
申请人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
发明人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1033 , G11C7/1075
摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
摘要翻译：本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可以将数据的半字节写入VRAM 。使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。

3. 发明授权

US5699314A Video random access memory device and method implementing independent two we nibble control 失效
标题翻译：视频随机存取存储器件和方法实现独立的两个我们的半字节控制
公开(公告)号：US5699314A
公开(公告)日：1997-12-16
申请号：US732943
申请日：1996-10-17
申请人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
发明人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1033 , G11C7/1075
摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
摘要翻译：本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可以将数据的半字节写入VRAM 。使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。

4. 发明授权

US5349247A Enhancement circuit and method for ensuring diactuation of a switching device 失效
标题翻译：用于确保开关装置的致动的增强电路和方法
公开(公告)号：US5349247A
公开(公告)日：1994-09-20
申请号：US893880
申请日：1992-06-05
申请人： Glen Hush , Mark R. Thomann
发明人： Glen Hush , Mark R. Thomann
IPC分类号： H03K19/017 , H03K14/20
CPC分类号： H03K19/01714
摘要： An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit gates the NMOS of the CMOS causing an incremental increase in CMOS drain current. The invention is an enhancement circuit for ensuring the deactuation of the pull-down portion of the push-pull arrangement during the action of the CMOS transistor arrangement.
摘要翻译： DRAM的输出驱动电路以推挽方式布线。 CMOS晶体管结构提供强大的输出信号。该晶体管装置包括推挽装置的上拉晶体管电路。自举电路使CMOS的NMOS栅极导通，使CMOS漏极电流增加。本发明是一种增强电路，用于确保在CMOS晶体管布置的作用期间推挽装置的下拉部分的去激活。

5. 发明授权

US5329186A CMOS bootstrapped output driver method and circuit 失效
标题翻译： CMOS自举输出驱动方法和电路
公开(公告)号：US5329186A
公开(公告)日：1994-07-12
申请号：US893879
申请日：1992-06-05
申请人： Glen Hush , Mark R. Thomann
发明人： Glen Hush , Mark R. Thomann
IPC分类号： H03K19/017 , H03K17/16
CPC分类号： H03K19/01714
摘要： An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit gates the NMOS of the CMOS causing an incremental increase in CMOS drain current.
摘要翻译： DRAM的输出驱动电路以推挽方式布线。 CMOS晶体管结构提供强大的输出信号。该晶体管装置包括推挽装置的上拉晶体管电路。自举电路使CMOS的NMOS栅极导通，使CMOS漏极电流增加。

6. 发明授权

US5128563A CMOS bootstrapped output driver method and circuit 失效
标题翻译： CMOS自举输出驱动方法和电路
公开(公告)号：US5128563A
公开(公告)日：1992-07-07
申请号：US619164
申请日：1990-11-28
申请人： Glen Hush , Mark R. Thomann
发明人： Glen Hush , Mark R. Thomann
IPC分类号： H03K19/017
CPC分类号： H03K19/01714
摘要： An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit gates the NMOS of the CMOS causing an incremental increase in CMOS drain current.
摘要翻译： DRAM的输出驱动电路以推挽方式布线。 CMOS晶体管结构提供强大的输出信号。该晶体管装置包括推挽装置的上拉晶体管电路。自举电路使CMOS的NMOS栅极导通，使CMOS漏极电流增加。

7. 发明授权

US07242603B2 Method of operating a complementary bit resistance memory sensor 失效
标题翻译：操作互补位电阻存储器传感器的方法
公开(公告)号：US07242603B2
公开(公告)日：2007-07-10
申请号：US11236562
申请日：2005-09-28
申请人： Glen Hush , Jake Baker
发明人： Glen Hush , Jake Baker
IPC分类号： G11C17/00
CPC分类号： G11C13/0011 , G11C7/062 , G11C11/16 , G11C13/004 , G11C2013/0042 , G11C2213/79
摘要： The present invention relates to a method and apparatus for sensing the resistance state of a programmable resistance memory, using complementary memory elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the resistance elements to determine the resistance state of an element being read.
摘要翻译：本发明涉及一种用于感测可编程电阻存储器的电阻状态的方法和装置，其使用互补存储器元件，一个保持正被感测的电阻状态，另一个保持互补电阻状态。感测放大器检测通过电阻元件放电的电压，以确定被读取的元件的电阻状态。

8. 发明申请

US20060099797A1 Integrated circuits with contemporaneously formed array electrodes and logic interconnects 审中-公开
标题翻译：具有同时形成的阵列电极和逻辑互连的集成电路
公开(公告)号：US20060099797A1
公开(公告)日：2006-05-11
申请号：US11315731
申请日：2005-12-22
申请人： Mirmajid Seyyedy , Glen Hush , Mark Tuttle , Terry Vollman
发明人： Mirmajid Seyyedy , Glen Hush , Mark Tuttle , Terry Vollman
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L27/228 , G11C5/06 , G11C11/14 , H01L27/105 , H01L27/10882 , H01L27/10897
摘要： The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.
摘要翻译：本发明涉及用于集成电路存储器件的互连。本发明的实施例包括以相对较少的步骤制造用于存储器件的互连的工艺。本发明的实施例还包括具有在芯片的不同区域中具有不等间距尺寸的金属化层的存储器件，从而允许在芯片的不同区域中同时制造阵列电极和电互连。这减少了用于制造互连的制造步骤的数量，从而加快制造并降低生产成本。

9. 发明申请

US20060083094A1 Method and apparatus for controlling refresh operations in a dynamic memory device 有权
公开(公告)号：US20060083094A1
公开(公告)日：2006-04-20
申请号：US11295856
申请日：2005-12-07
申请人： Manoj Sinha , Glen Hush
发明人： Manoj Sinha , Glen Hush
IPC分类号： G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for increased leakage at higher temperatures and more closely tailor the timing of the refresh operations to the conditions of the dynamic memory device.

10. 发明授权

US06954385B2 Method and apparatus for sensing resistive memory state 有权
标题翻译：用于感测电阻式存储器状态的方法和装置
公开(公告)号：US06954385B2
公开(公告)日：2005-10-11
申请号：US10918386
申请日：2004-08-16
申请人： Stephen L. Casper , Kevin Duesman , Glen Hush
发明人： Stephen L. Casper , Kevin Duesman , Glen Hush
IPC分类号： G11C13/00 , G11C11/34 , G11C13/02 , G11C16/28 , H01L27/105
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2013/0054 , G11C2013/009 , G11C2213/79
摘要： A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
摘要翻译：提供了用于读取可编程导体随机存取存储器（PCRAM）单元的电阻电平的读出电路。通过从升高的行线电压激活存取晶体管，通过PCRAM单元引入电压电位差。数字线和数位补码参考线都被预充电到第一预定电压。被感测的电池具有通过PCRAM单元的可编程导体存储元件的电阻放电的预充电电压。比较在数字线和参考导体读取的电压。如果数字线上的电压大于参考电压，则将单元读为高电阻值（例如，逻辑高电平）; 然而，如果在数字线处测量的电压低于参考电压的电压，则将该单元读为低电阻值（例如，逻辑低电平）。

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