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1. 发明授权

US5704014A Voltage-current conversion circuit employing MOS transistor cells as synapses of neural network 失效
标题翻译：采用MOS晶体管电池的电压 - 电流转换电路作为神经网络的突触
公开(公告)号：US5704014A
公开(公告)日：1997-12-30
申请号：US828063
申请日：1992-01-30
申请人： Giulio Marotta , Eros Pasero
发明人： Giulio Marotta , Eros Pasero
IPC分类号： G06N3/063 , H03K19/0948 , G06F15/18
CPC分类号： G06N3/0635
摘要： A cell of MOS transistors for converting a voltage into a current for forming synapses of neural nets, in particular for converting the difference between an input voltage (V.sub.IN) and a voltage (V.sub.W) for weighting the synapse into a current, realized by means of a differential stage comprising a first transistor (M1) operating as a current generator, in which a first and a second branch in parallel end, which branches respectively comprise a second (M2) and a third (M3) push-pull connected transistor, to the gate regions of which the input voltage (V.sub.IN) and the voltage (V.sub.W) for weighting the synapse, and to which a fourth (M4) and a fifth (M5) transistor are respectively connected in series, in which the fourth (M4) and the fifth (M5) transistor are P-MOS transistors having their gate regions short-circuited and said fourth (M4) P-MOS transistor is connected as a diode, and in which the output current (I.sub.OUT) is drawn from the node (N) that connects said third (M3) and said fifth (M5) transistors inserted in series in said second branch of the circuit and a capacitor (c) is connected to the gate region of said third (M3) transistor to store the voltage (V.sub.W) for weighting the synapse applied to the circuit.
摘要翻译：用于将电压转换成用于形成神经网络突触的电流的MOS晶体管的单元，特别是用于将用于加权突触的输入电压（VIN）和电压（VW）之间的差值转换成电流，所述电压通过差动级包括作为电流发生器工作的第一晶体管（M1），其中并联端的第一和第二支路分别分别包括第二（M2）和第三（M3）推挽连接的晶体管，至其输入电压（VIN）和用于加权突触的电压（VW）的栅极区域和第四（M4）和第五（M5）晶体管分别串联连接的栅极区域，其中第四（M4）并且第五（M5）晶体管是其栅极区短路的P-MOS晶体管，并且所述第四（M4）P-MOS晶体管作为二极管连接，并且其中输出电流（IOUT）从节点 N），其连接所述第三（M3）和所述第五（M5）转换器串联插入电路的所述第二分支的电阻器和电容器（c）连接到所述第三（M3）晶体管的栅极区域，以存储用于加权施加到电路的突触的电压（VW）。

2. 发明授权

US5457771A Integrated circuit with non-volatile, variable resistor, for use in neuronic network 失效
标题翻译：具有非易失性，可变电阻的集成电路，用于神经网络
公开(公告)号：US5457771A
公开(公告)日：1995-10-10
申请号：US762817
申请日：1991-09-18
申请人： Giuliano Imondi , Giulio Marotta , Eros Pasero , Giulio Porrovecchio , Giuseppe Savarese
发明人： Giuliano Imondi , Giulio Marotta , Eros Pasero , Giulio Porrovecchio , Giuseppe Savarese
IPC分类号： G11C11/54 , G06N3/063 , G11C16/04 , G11C17/00 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/86
CPC分类号： G06N3/0635 , H01L27/105 , H01L27/115
摘要： Integrated circuit with a non-volatile variable resistor which is particularly adapted for use in a neuronic network. The integrated circuit comprises a symmetrically replicated structure including a floating gate MOS transistor (TRP; TRN) and an EEPROM memory cell based upon N-channel MOS transistors and including a read-out MOS transistor (TSP; TSN) and a tunnel-effect charge injection MOS element (TUNP; TUNN), with floating gates. The floating gates of all transistors and of the tunnel-effect element are connected together, with the ends of the resistor (R1P, R2P; R1N, R2N) being taken out from the source and drain regions of the floating gate MOS transistor.
摘要翻译：具有非易失性可变电阻器的集成电路，其特别适用于神经网络。集成电路包括对称复制结构，包括浮置栅极MOS晶体管（TRP; TRN）和基于N沟道MOS晶体管的EEPROM存储单元，并且包括读出的MOS晶体管（TSP; TSN）和隧道效应电荷注入MOS元件（TUNP; TUNN），带浮动栅极。所有晶体管和隧道效应元件的浮置栅极连接在一起，电阻（R1P，R2P; R1N，R2N）的端部从浮置栅极MOS晶体管的源极和漏极区域中取出。

3. 发明申请

US20050017791A1 Metal-poly integrated capacitor structure 有权
公开(公告)号：US20050017791A1
公开(公告)日：2005-01-27
申请号：US10921396
申请日：2004-08-19
申请人： Giulio Marotta
发明人： Giulio Marotta
IPC分类号： G11C5/14 , G11C16/30 , H01L27/08 , H01L27/148 , H04L12/413
CPC分类号： H01L27/0805 , G11C5/145 , G11C16/30 , H01L23/5223 , H01L27/0222 , H01L27/105 , H01L27/11526 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.

4. 发明授权

US5732021A Programmable and convertible non-volatile memory array 失效
标题翻译：可编程和可转换的非易失性存储器阵列
公开(公告)号：US5732021A
公开(公告)日：1998-03-24
申请号：US690244
申请日：1996-07-19
申请人： Michael C. Smayling , Giulio Marotta , Giovanni Santin , Pietro Piersimoni , Cristina Lattaro
发明人： Michael C. Smayling , Giulio Marotta , Giovanni Santin , Pietro Piersimoni , Cristina Lattaro
IPC分类号： G11C16/12 , G11C16/16 , H01L21/8247 , H01L27/105 , G11C7/00
CPC分类号： H01L27/11526 , G11C16/12 , G11C16/16 , H01L27/105 , H01L27/11546
摘要： A method for selectibly erasing one or more non-volatile programmable memory cells in an integrated circuit. The method is applicable to an array 1 of memory cells 10 fabricated in a semiconductor substrate 30 of a first conductivity type semiconductor material, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. The cells should be formed in a first well 33 of said first conductivity type semiconductor material, the first wells being formed in second wells 31 of a second conductivity type semiconductor material, the first wells including cells in groups of one or more. The method involves the steps of applying a high voltage source to a selected one or more column lines, applying a zero voltage source to a selected one or more row lines; and applying the high voltage source to non-selected row lines. The method is particularly suited to Flash memories. Erasure can be sectored by grouping cells in separate ones of the first wells and applying the method selectably to such groups.
摘要翻译：一种用于可选地擦除集成电路中的一个或多个非易失性可编程存储器单元的方法。该方法适用于在第一导电型半导体材料的半导体衬底30中制造的存储器单元10的阵列1，每个单元具有用于对单元进行编程的浮置栅极14和用于读取该单元的控制栅极11，该阵列具有多条行线15，多条列线25和多条输出线18.这些电池应形成在所述第一导电类型半导体材料的第一阱33中，第一阱形成在第一阱31中第二导电型半导体材料，第一阱包括一个或多个基团的单元。该方法包括以下步骤：将高电压源施加到所选择的一个或多个列线，将零电压源施加到所选择的一个或多个行线; 以及将高电压源施加到未选择的行线。该方法特别适用于闪存。可以通过将单元格分组在第一个孔中并将该方法可选择地应用于这样的组来分割擦除。

5. 发明授权

US5717634A Programmable and convertible non-volatile memory array 失效
标题翻译：可编程和可转换的非易失性存储器阵列
公开(公告)号：US5717634A
公开(公告)日：1998-02-10
申请号：US684650
申请日：1996-07-19
申请人： Michael C. Smayling , Giulio Marotta , Giovanni Santin , Pietro Piersimoni
发明人： Michael C. Smayling , Giulio Marotta , Giovanni Santin , Pietro Piersimoni
IPC分类号： G11C16/08 , G11C16/10 , G11C17/12 , H01L21/8247 , H01L27/105 , G11C16/06
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C17/12 , H01L27/105 , H01L27/11546
摘要： A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected. The decoder circuit also includes a high power pass device 82 associated with each row line, having one of its source and drain connected to the associated row node, having the other of its source and drain connected to a row line and having its gate connected to a first voltage, lower than the high voltage, so as to couple the signal on the row node to the row line. Finally, a keeper circuit 102 is provided, associated with each row line and coupled to the high voltage for sensing the signal on the row line and in response thereto for coupling the high voltage to the row line. The memory has high speed, since the decoder logic is performed by low power devices. In addition, in fabrication the memory is readily convertible to a permanent ROM by eliminating the formation of the floating gate, bypassing the high power pass device and not connecting the keeper circuit.
摘要翻译：诸如闪存EPROM的非易失性集成电路存储器，包括存储器单元10的阵列1，每个单元具有用于对单元进行编程的浮置栅极14和用于读取单元的控制栅极11，该阵列具有多个行列15，多列列线25和多条输出线18.包括解码器电路16，其具有用于阵列中的每一行的多条输入线94,96，并具有作为输出的行线15 解码器电路包括与每条行线相关联的解码器逻辑电路，解码器逻辑电路包括多个低功率逻辑器件84-90，其互连以对输入线上的信号执行预定的解码功能，用于相关联的行线到当解码器逻辑电路确定相关联的行线被选择时，将信号施加到相关联的行节点。解码器电路还包括与每个行线相关联的高功率通过器件82，其中源极和漏极中的一个源极和漏极连接到相关联的行节点，其另一个源极和漏极连接到行线并且其栅极连接到低于高电压的第一电压，以将行节点上的信号耦合到行线。最后，提供一个保持器电路102，其与每个行线相关联并耦合到高电压，用于感测行线上的信号，并响应于此将高电压耦合到行线。存储器具有高速度，因为解码器逻辑由低功率器件执行。此外，在制造中，通过消除浮动栅极的形成，绕过高功率通过装置并且不连接保持器电路，存储器容易地转换成永久ROM。

6. 发明授权

US08407400B2 Dynamic SLC/MLC blocks allocations for non-volatile memory 有权
标题翻译：动态SLC / MLC阻止非易失性存储器的分配
公开(公告)号：US08407400B2
公开(公告)日：2013-03-26
申请号：US12269766
申请日：2008-11-12
申请人： Giulio Marotta , Luca De Santis , Tommaso Vali
发明人： Giulio Marotta , Luca De Santis , Tommaso Vali
IPC分类号： G06F12/00
CPC分类号： G11C16/16 , G06F12/0246 , G06F2212/7202 , G11C2211/5641
摘要： Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.
摘要翻译：公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。当内存使用量低时，使用SLC模式。当内存使用率高时，使用MLC模式。动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。

7. 发明申请

US20060261853A1 Output buffer strength trimming 有权
公开(公告)号：US20060261853A1
公开(公告)日：2006-11-23
申请号：US11415980
申请日：2006-05-02
申请人： Girolamo Gallo , Giulio Marotta , Giovanni Naso
发明人： Girolamo Gallo , Giulio Marotta , Giovanni Naso
IPC分类号： H03K19/094
CPC分类号： H03K17/164
摘要： Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.

8. 发明申请

US20050280049A1 Metal-poly integrated capacitor structure 审中-公开
标题翻译：金属多晶集成电容器结构
公开(公告)号：US20050280049A1
公开(公告)日：2005-12-22
申请号：US11211202
申请日：2005-08-25
申请人： Giulio Marotta
发明人： Giulio Marotta
IPC分类号： G11C5/14 , G11C16/30 , H01L27/08 , H01L27/148
CPC分类号： H01L27/0805 , G11C5/145 , G11C16/30 , H01L23/5223 , H01L27/0222 , H01L27/105 , H01L27/11526 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between the poly silicon layer and the second metal layer. The first metal layer has a first terminal and a second terminal. The first terminal is electrically isolated from the second terminal.
摘要翻译：可用于非易失性存储器的电荷泵电路中的金属 - 多晶集成电容器结构。在一个实施例中，电容器包括多晶硅层，第一金属层和第二金属层。第一金属层位于多晶硅层和第二金属层之间。第一金属层具有第一端子和第二端子。第一端子与第二端子电隔离。

9. 发明申请

US20050231245A1 Conditioned and robust ultra-low power power-on reset sequencer for integrated circuits 失效
标题翻译：用于集成电路的条件稳健的超低功耗上电复位定序器
公开(公告)号：US20050231245A1
公开(公告)日：2005-10-20
申请号：US11157267
申请日：2005-06-21
申请人： Giulio Marotta
发明人： Giulio Marotta
IPC分类号： H03K17/22 , H03L7/00
CPC分类号： H03K17/223
摘要： A power-on reset (POR) circuit determines when integrated circuit voltages and/or currents have reached predetermined levels and provides trigger signals to control the POR transition of the integrated circuit.
摘要翻译：上电复位（POR）电路确定集成电路电压和/或电流何时达到预定电平，并提供触发信号来控制集成电路的POR转换。

10. 发明申请

US20050024951A1 Voltage and temperature compensated pulse generator 有权
公开(公告)号：US20050024951A1
公开(公告)日：2005-02-03
申请号：US10932858
申请日：2004-09-02
申请人： Giulio Marotta , Tommaso Vali
发明人： Giulio Marotta , Tommaso Vali
IPC分类号： G11C7/22 , G11C16/32 , H03K3/011 , H03K3/0231 , H03K4/50 , G11C16/04
CPC分类号： G11C7/04 , G11C7/22 , G11C7/222 , G11C16/32 , H03K3/011 , H03K3/0231 , H03K4/50
摘要： Ramp comparator pulse generators having temperature and voltage compensation are adapted for use in integrated circuit devices such as memory devices. Such pulse generators include a ramp signal generator, a threshold signal generator, and a comparator providing an output signal in response to a difference between the potential level of the threshold signal and the potential level of the ramp signal. The pulse generators described herein utilize an adaptive threshold signal generator configured as a voltage divider and having resistive components having differing effective temperature coefficients of resistivity. The adaptive threshold signal generator has an upper resistive component and a lower resistive component coupled in series between a high potential node and a low potential node. The lower resistive component has an effective temperature coefficient of resistivity that is less than an effective temperature coefficient of resistivity of the upper resistive component.

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