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1. 发明授权

US07235438B2 Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects 有权
标题翻译：在二氧化硅 - 碳化硅界面处纳入氮以钝化界面缺陷
公开(公告)号：US07235438B2
公开(公告)日：2007-06-26
申请号：US11122474
申请日：2005-05-05
申请人： Gilyong Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano Di Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
发明人： Gilyong Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano Di Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
IPC分类号： H01L21/3105
CPC分类号： H01L21/3145 , H01L21/0214 , H01L21/02164 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/045 , H01L21/049 , H01L21/31658 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/66068 , Y10S438/931
摘要： In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.In another aspect, the present invention provides a silicon carbide semiconductor device that has a 4H-silicon carbide substrate, a layer of silicon dioxide disposed on the 4H-silicon carbide substrate and a region of substantial nitrogen concentration at the silicon dioxide/silicon carbide interface.
摘要翻译：一方面，本发明提供一种制造碳化硅半导体器件的方法。在碳化硅衬底上形成二氧化硅层，并且在二氧化硅/碳化硅界面上并入氮。在一个实施方案中，通过在一氧化氮或一氧化二氮中对半导体器件退火来引入氮。在另一个实施方案中，通过用氨将半导体器件退火而并入氮气。另一方面，本发明提供一种碳化硅半导体器件，其具有4H-碳化硅衬底，设置在4H-碳化硅衬底上的二氧化硅层和在二氧化硅/碳化硅界面处具有显着的氮浓度的区域。

2. 发明授权

US06939756B1 Inclusion of nitrogen at the silicon dioxide-silicon carbide interace for passivation of interface defects 有权
标题翻译：在二氧化硅 - 碳化硅界面处纳入氮以钝化界面缺陷
公开(公告)号：US06939756B1
公开(公告)日：2005-09-06
申请号：US09818193
申请日：2001-03-26
申请人： Gilyong Chung , Chin Che Tin , John R. Williams , Kyle McDonald , Massimiliano Di Ventra , Robert A. Weller , Sokrates T. Pantelides , Leonard C. Feldman
发明人： Gilyong Chung , Chin Che Tin , John R. Williams , Kyle McDonald , Massimiliano Di Ventra , Robert A. Weller , Sokrates T. Pantelides , Leonard C. Feldman
IPC分类号： H01L21/04 , H01L21/3115
CPC分类号： H01L21/3145 , H01L21/0214 , H01L21/02164 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/045 , H01L21/049 , H01L21/31658 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/66068 , Y10S438/931
摘要： A method for manufacturing a silicon carbide semiconductor device. In one embodiment, the method includes the following steps: a layer of silicon dioxide is formed on a silicon carbide substrate to create a silicon dioxide/silicon carbide interface and then nitrogen is incorporated at the silicon dioxide/silicon carbide interface for reduction in an interface trap density. The silicon carbide substrate, in one embodiment, includes a n-type 4H-silicon carbide.
摘要翻译：一种制造碳化硅半导体器件的方法。在一个实施例中，该方法包括以下步骤：在碳化硅衬底上形成一层二氧化硅以产生二氧化硅/碳化硅界面，然后在二氧化硅/碳化硅界面处并入氮以还原界面陷阱密度。在一个实施例中，碳化硅衬底包括n型4H-碳化硅。

3. 发明申请

US20080128709A1 Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects 有权
标题翻译：在二氧化硅 - 碳化硅界面处纳入氮以钝化界面缺陷
公开(公告)号：US20080128709A1
公开(公告)日：2008-06-05
申请号：US11811396
申请日：2007-06-08
申请人： Gilyong Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano De Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
发明人： Gilyong Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano De Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
IPC分类号： H01L29/24
CPC分类号： H01L21/3145 , H01L21/0214 , H01L21/02164 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/045 , H01L21/049 , H01L21/31658 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/66068 , Y10S438/931
摘要： In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.In another aspect, the present invention provides a silicon carbide semiconductor device that has a 4H-silicon carbide substrate, a layer of silicon dioxide disposed on the 4H-silicon carbide substrate and a region of substantial nitrogen concentration at the silicon dioxide/silicon carbide interface.
摘要翻译：一方面，本发明提供一种制造碳化硅半导体器件的方法。在碳化硅衬底上形成二氧化硅层，并且在二氧化硅/碳化硅界面上并入氮。在一个实施方案中，通过在一氧化氮或一氧化二氮中对半导体器件退火来引入氮。在另一个实施方案中，通过用氨将半导体器件退火而并入氮气。另一方面，本发明提供一种碳化硅半导体器件，其具有4H-碳化硅衬底，设置在4H-碳化硅衬底上的二氧化硅层和在二氧化硅/碳化硅界面处具有显着的氮浓度的区域。

4. 发明授权

US07727340B2 Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects 有权
标题翻译：在二氧化硅 - 碳化硅界面处纳入氮以钝化界面缺陷
公开(公告)号：US07727340B2
公开(公告)日：2010-06-01
申请号：US11811396
申请日：2007-06-08
申请人： Gilyong Y. Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano De Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
发明人： Gilyong Y. Chung , Chin-Che Tin , John R. Williams , Kyle McDonald , Massimiliano De Ventra , Robert A. Weller , Socrates T. Pantelides , Leonard C. Feldman
IPC分类号： H01L21/3105
CPC分类号： H01L21/3145 , H01L21/0214 , H01L21/02164 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/045 , H01L21/049 , H01L21/31658 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/66068 , Y10S438/931
摘要： In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one embodiment, nitrogen is incorporated by annealing the semiconductor device in nitric oxide or nitrous oxide. In another embodiment, nitrogen is incorporated by annealing the semiconductor device in ammonia.
摘要翻译：一方面，本发明提供一种制造碳化硅半导体器件的方法。在碳化硅衬底上形成二氧化硅层，并且在二氧化硅/碳化硅界面上并入氮。在一个实施方案中，通过在一氧化氮或一氧化二氮中对半导体器件进行退火来引入氮。在另一个实施方案中，通过用氨将半导体器件退火而并入氮气。

5. 发明申请

US20150318358A1 Semiconductor Devices Including Polar Insulation Layer Capped by Non-Polar Insulation Layer 有权
标题翻译：包括非极性绝缘层覆盖的极性绝缘层的半导体器件
公开(公告)号：US20150318358A1
公开(公告)日：2015-11-05
申请号：US14800694
申请日：2015-07-15
申请人： John R. Williams , Ayayi C. Ahyi , Tamara F. Isaacs-Smith , Yogesh K. Sharma , Leonard C. Feldman
发明人： John R. Williams , Ayayi C. Ahyi , Tamara F. Isaacs-Smith , Yogesh K. Sharma , Leonard C. Feldman
IPC分类号： H01L29/16 , H01L21/04 , H01L21/02 , H01L29/51 , H01L29/423
CPC分类号： H01L29/1608 , H01L21/02129 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/02321 , H01L21/045 , H01L21/049 , H01L29/42364 , H01L29/513 , H01L29/517 , H01L29/78
摘要： Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.
摘要翻译：公开了包括由非极性绝缘层覆盖的极性绝缘层的半导体器件的说明性实施例，以及制造这种半导体器件的方法。在至少一个说明性实施例中，半导体器件可以包括半导体衬底，设置在半导体衬底上的极性绝缘层，并且包括配置成增加半导体衬底的至少一部分中的载流子迁移率的第V族元件，极性绝缘层设置在极性绝缘层之上。

6. 发明申请

US20140077227A1 Semiconductor Devices Including Polar Insulation Layer Capped By Non-Polar Insulation Layer 有权
标题翻译：包括非极性绝缘层覆盖的极性绝缘层的半导体器件
公开(公告)号：US20140077227A1
公开(公告)日：2014-03-20
申请号：US14027817
申请日：2013-09-16
申请人： John R. Williams , Ayayi C. Ahyi , Tamara F. Isaacs-Smith , Yogesh K. Sharma , Leonard C. Feldman
发明人： John R. Williams , Ayayi C. Ahyi , Tamara F. Isaacs-Smith , Yogesh K. Sharma , Leonard C. Feldman
IPC分类号： H01L29/51
CPC分类号： H01L29/1608 , H01L21/02129 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/02321 , H01L21/045 , H01L21/049 , H01L29/42364 , H01L29/513 , H01L29/517 , H01L29/78
摘要： Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.
摘要翻译：公开了包括由非极性绝缘层覆盖的极性绝缘层的半导体器件的说明性实施例，以及制造这种半导体器件的方法。在至少一个说明性实施例中，半导体器件可以包括半导体衬底，设置在半导体衬底上的极性绝缘层，并且包括配置成增加半导体衬底的至少一部分中的载流子迁移率的第V族元件，极性绝缘层设置在极性绝缘层之上。

7. 发明授权

US09117817B2 Semiconductor devices including polar insulation layer capped by non-polar insulation layer 有权
标题翻译：半导体器件包括非极性绝缘层覆盖极性绝缘层
公开(公告)号：US09117817B2
公开(公告)日：2015-08-25
申请号：US14027817
申请日：2013-09-16
申请人： John R. Williams , Ayayi C. Ahyi , Tamara F. Isaacs-Smith , Yogesh K. Sharma , Leonard C. Feldman
发明人： John R. Williams , Ayayi C. Ahyi , Tamara F. Isaacs-Smith , Yogesh K. Sharma , Leonard C. Feldman
IPC分类号： H01L21/336 , H01L29/51 , H01L21/04 , H01L29/78
CPC分类号： H01L29/1608 , H01L21/02129 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/02321 , H01L21/045 , H01L21/049 , H01L29/42364 , H01L29/513 , H01L29/517 , H01L29/78
摘要： Illustrative embodiments of semiconductor devices including a polar insulation layer capped by a non-polar insulation layer, and methods of fabrication of such semiconductor devices, are disclosed. In at least one illustrative embodiment, a semiconductor device may comprise a semiconductor substrate, a polar insulation layer disposed on the semiconductor substrate and comprising a Group V element configured to increase a carrier mobility in at least a portion of the semiconductor substrate, and a non-polar insulation layer disposed above the polar insulation layer.
摘要翻译：公开了包括由非极性绝缘层覆盖的极性绝缘层的半导体器件的说明性实施例以及制造这种半导体器件的方法。在至少一个说明性实施例中，半导体器件可以包括半导体衬底，设置在半导体衬底上的极性绝缘层，并且包括配置成增加半导体衬底的至少一部分中的载流子迁移率的第V族元件，极性绝缘层设置在极性绝缘层之上。

8. 发明授权

US5532510A Reverse side etching for producing layers with strain variation 失效
标题翻译：用于生产具有应变变化的层的反面蚀刻
公开(公告)号：US5532510A
公开(公告)日：1996-07-02
申请号：US366515
申请日：1994-12-30
申请人： Netzer Amorai-Moriya , Igal M. Brener , Leonard C. Feldman
发明人： Netzer Amorai-Moriya , Igal M. Brener , Leonard C. Feldman
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/335 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： B82Y10/00 , H01L29/66469
摘要： A new method to fabricate strain patterns on a strained semiconductor structure, is disclosed. The method is based on the new concept of reverse side etching of a laterally homogeneous, strained structure so that strain changes can be induced in the front-side, pre-strained area as a result of the reverse side etching process. Semiconductor structures such as quantum-wires, quantum dots, and quantum well devices may be formed by the disclosed methods where the reverse side etching provides strain control of the material properties of the semiconductor structure without processing the front side which is generally the active and the most sensitive region of the semiconductor structure. Such semiconductor structures can be formed by a process including the steps of forming a strained layer on the front-side of the structure, and etching the reverse side of the substrate to form a pattern of strain into the front-side, thus forming selectively strained regions.
摘要翻译：公开了一种在应变半导体结构上制造应变图案的新方法。该方法基于横向均匀的应变结构的逆向蚀刻的新概念，使得由于反向侧蚀刻工艺可以在前侧，预应变区域中引起应变变化。半导体结构如量子线，量子点和量子阱器件可以通过所公开的方法形成，其中反向蚀刻提供对半导体结构的材料性质的应变控制，而不需要处理通常为有源的正面和最敏感的半导体结构区域。这种半导体结构可以通过以下步骤形成，该方法包括以下步骤：在结构的前侧形成应变层，并蚀刻基板的反面以在前侧形成应变图案，从而形成选择性应变地区。

9. 发明授权

US5500391A Method for making a semiconductor device including diffusion control 失效
标题翻译：制造包括扩散控制的半导体器件的方法
公开(公告)号：US5500391A
公开(公告)日：1996-03-19
申请号：US287989
申请日：1994-08-09
申请人： Joze Bevk , Leonard C. Feldman , Hans-Joachim L. Gossmann , Henry S. Luftman , Ran-Hong Yan
发明人： Joze Bevk , Leonard C. Feldman , Hans-Joachim L. Gossmann , Henry S. Luftman , Ran-Hong Yan
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/161
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/823807 , H01L29/1079 , Y10S438/981
摘要： A process for making a MOS device on a silicon substrate includes the step of forming a buried layer of germanium-silicon alloy in the substrate, or, alternatively, a buried layer of silicon enclosed between thin, germanium-rich layers. This buried layer is doped with boron, and tends to confine the boron during annealing and oxidation steps. The process includes a step of exposing the substrate to an oxidizing atmosphere such that an oxide layer 10 .ANG.-500 .ANG. thick is grown on the substrate.
摘要翻译：在硅衬底上制造MOS器件的工艺包括在衬底中形成锗 - 硅合金掩埋层的步骤，或者替代地，在薄富锗层之间封装硅掩埋层。该掩埋层掺杂硼，并且倾向于在退火和氧化步骤期间限制硼。该方法包括将衬底暴露于氧化气氛的步骤，使得在衬底上生长厚度超过-500埃的厚度的氧化物层。

10. 发明授权

US5068868A Vertical cavity surface emitting lasers with electrically conducting mirrors 失效
标题翻译：带导电镜的垂直孔表面发射激光
公开(公告)号：US5068868A
公开(公告)日：1991-11-26
申请号：US526204
申请日：1990-05-21
申请人： Dennis G. Deppe , Leonard C. Feldman , Rose F. Kopf , Erdmann F. Schubert , Li Wei Tu , George J. Zydzik
发明人： Dennis G. Deppe , Leonard C. Feldman , Rose F. Kopf , Erdmann F. Schubert , Li Wei Tu , George J. Zydzik
IPC分类号： H01S5/00 , H01S5/042 , H01S5/183
CPC分类号： H01S5/18361 , H01S5/18375 , H01S5/18377 , H01S5/18394
摘要： This invention is a semiconductor vertical cavity surface emitting laser comprising a lasing cavity with an active layer, a bottom (rear) mirror and a top (front) mirror, and a front and rear electrodes for applying excitation current in direction substantially parallel to the direction of optical propagation. In accordance with this invention the front mirror comprises a thin, semitransparent metal layer which also acts as the front electrode. The metal layer is upon a highly doped layer forming a non-alloyed ohmic contact. The metal is selected from Ag and Al and is deposited in thickness ranging from 5 to 55 nm. The VCSEL is a semiconductor device wherein the semiconductor material is a III-V or II-VI compound semiconductor. For a VCSEL with GaAs active layer, the light output from the front metal mirror/electrode side yields a high external differential quantum efficiency as high as 54 percent. This is the highest quantum efficiency obtained in VCSEL structures. Quantum efficiencies on the oder of 10 to 30 percent are typical for prior art VCSEL structures. The VCSEL is suitable for fabrication utilizing planar technology.

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