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1. 发明授权

US06550013B1 Memory clock generator and method therefor 失效
标题翻译：内存时钟发生器及其方法
公开(公告)号：US06550013B1
公开(公告)日：2003-04-15
申请号：US09388952
申请日：1999-09-02
申请人： Gilles Gervais , James D. Wagoner , Stephen D. Weitzel
发明人： Gilles Gervais , James D. Wagoner , Stephen D. Weitzel
IPC分类号： G06F108
CPC分类号： G06F1/08
摘要： A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift register. A set of outputs tapped off of the shift register is decoded, along with a plurality of control signals, in AND-OR logic to generate a clock output, which may run at a predetermined multiple of the memory clock rate. The clock output may have one of a plurality of ratios of memory clock period to processor clock period. The control signals select the ratio. The clock generator may be started asynchronously, and, additionally, the generator outputs a signal to the processor having an edge that has a predetermined temporal relationship with the start of the clock generator.
摘要翻译：实现了存储器时钟发生器装置和方法。从处理器时钟产生存储器时钟“开环”。处理器时钟被选通并通过移位寄存器传播。从移位寄存器中抽出的一组输出与多个控制信号一起被解码，并且以“或”逻辑进行解码，以生成可以以存储器时钟速率的预定倍数运行的时钟输出。时钟输出可以具有存储器时钟周期与处理器时钟周期的多个比率中的一个。控制信号选择比例。时钟发生器可以异步启动，并且另外，发生器向具有与时钟发生器的开始具有预定时间关系的边沿的处理器输出信号。

2. 发明授权

US07469357B2 Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control 失效
标题翻译：使用流水线流量控制的执行单元中动态功率管理的方法和装置
公开(公告)号：US07469357B2
公开(公告)日：2008-12-23
申请号：US11552790
申请日：2006-10-25
申请人： Christopher Michael Abernathy , Gilles Gervais , Rolf Hilgendork
发明人： Christopher Michael Abernathy , Gilles Gervais , Rolf Hilgendork
IPC分类号： G06F1/04
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152
摘要： Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.
摘要翻译：通过动态地将时钟施加到微处理器流水线中的执行单元来节省功率。仅当执行单元的指令有效时才应用执行单元的时钟。在执行单元不需要运行的其他时间，时钟不被应用于执行单元。在本发明的优选实施例中，动态时钟控制单元用于向本地时钟缓冲器提供控制信号，以向执行单元提供本地时钟。

3. 发明申请

US20070300082A1 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US20070300082A1
公开(公告)日：2007-12-27
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

4. 发明授权

US07137013B2 Method and apparatus for dynamic power management in an execution unit using pipeline wave flow control 失效
公开(公告)号：US07137013B2
公开(公告)日：2006-11-14
申请号：US10042082
申请日：2002-01-07
申请人： Christopher Michael Abernathy , Gilles Gervais , Rolf Hilgendork
发明人： Christopher Michael Abernathy , Gilles Gervais , Rolf Hilgendork
IPC分类号： G06F1/04
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152
摘要： Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.

5. 发明授权

US07739573B2 Voltage identifier sorting 有权
标题翻译：电压标识符排序
公开(公告)号：US07739573B2
公开(公告)日：2010-06-15
申请号：US11621766
申请日：2007-01-10
申请人： Jonathan J. DeMent , Sang H. Dhong , Gilles Gervais , Alain Loiseau , Kirk D. Peterson , John L. Sinchak
发明人： Jonathan J. DeMent , Sang H. Dhong , Gilles Gervais , Alain Loiseau , Kirk D. Peterson , John L. Sinchak
IPC分类号： G01R31/30
CPC分类号： G01R31/3004 , G01R31/31721 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.
摘要翻译：提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

6. 发明申请

US20090112550A1 System and Method for Generating a Worst Case Current Waveform for Testing of Integrated Circuit Devices 有权
标题翻译：用于生成最差情况的系统和方法用于集成电路器件测试的电流波形
公开(公告)号：US20090112550A1
公开(公告)日：2009-04-30
申请号：US11927840
申请日：2007-10-30
申请人： Makoto Aikawa , Jonathan J. DeMent , Sang H. Dhong , Brian K. Flachs , Gilles Gervais , Iwao Takiguchi , Tetsuji Tamura
发明人： Makoto Aikawa , Jonathan J. DeMent , Sang H. Dhong , Brian K. Flachs , Gilles Gervais , Iwao Takiguchi , Tetsuji Tamura
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/318364
摘要： A system and method for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.
摘要翻译：提供一种用于产生用于集成电路器件测试的最坏情况电流波形的系统和方法。首先执行集成电路装置的结构分析，以确定要应用于集成电路装置的初始最坏情况功率工作负荷。此后，将得到的最坏情况功率工作量应用于模型，并且被模拟以产生输入到集成电路器件的电气模型以产生最坏情况噪声预算值的最坏情况电流波形。然后将最坏情况的噪声预算值与从最坏情况功率工作负载应用于硬件实现的集成电路设备的测量噪声进行比较。可以选择最坏情况下的电流波形以用于集成电路设备的未来测试，或者可以对仿真模型进行修改，并且基于比较的结果重复该过程。

7. 发明申请

US20090044030A1 APPARATUS FOR DYNAMIC POWER MANAGEMENT IN AN EXECUTION UNIT USING PIPELINE WAVE FLOW CONTROL 失效
标题翻译：使用管道流量控制在执行单元中进行动态电源管理的装置
公开(公告)号：US20090044030A1
公开(公告)日：2009-02-12
申请号：US12245880
申请日：2008-10-06
申请人： Christopher Michael Abernathy , Gilles Gervais , Rolf Hilgendorf
发明人： Christopher Michael Abernathy , Gilles Gervais , Rolf Hilgendorf
IPC分类号： G06F1/04
CPC分类号： G06F1/3243 , G06F1/3203 , Y02D10/152
摘要： Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamic clock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.
摘要翻译：通过动态地将时钟施加到微处理器流水线中的执行单元来节省功率。仅当执行单元的指令有效时才应用执行单元的时钟。在执行单元不需要运行的其他时间，时钟不被应用于执行单元。在本发明的优选实施例中，动态时钟控制单元用于向本地时钟缓冲器提供控制信号，以向执行单元提供本地时钟。

8. 发明申请

US20080189090A1 System and Method for Determining a Guard Band for an Operating Voltage of an Integrated Circuit Device 审中-公开
标题翻译：用于确定集成电路装置的工作电压的保护带的系统和方法
公开(公告)号：US20080189090A1
公开(公告)日：2008-08-07
申请号：US11671852
申请日：2007-02-06
申请人： Makoto Aikawa , Sang H. Dhong , Brian Flachs , Gilles Gervais , Yoichi Nishino , Iwao Takiguchi , Tetsuji Tamura , Yaping Zhou
发明人： Makoto Aikawa , Sang H. Dhong , Brian Flachs , Gilles Gervais , Yoichi Nishino , Iwao Takiguchi , Tetsuji Tamura , Yaping Zhou
IPC分类号： G06G7/62 , G06F17/50
CPC分类号： G06F17/5036 , G01R31/318357
摘要： A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.
摘要翻译：提供了一种用于确定集成电路装置的工作电压的保护带的系统和方法。该系统和方法提供了一种基于使用最差情况波形刺激从集成电路装置的模拟获得的模拟噪声与可能是工作负载/测试模式的模拟或测量的电源噪声的比较来计算保护频带的机制使用测试设备实现。通过将工作负载/测试模式的仿真结果与应用于集成电路设备的硬件实现的工作负载/测试模式的测量结果进行比较来确定保护频带的缩放因子。该缩放因子被应用于通过模拟工作负载/测试模式产生的噪声与通过模拟最坏情况电流波形产生的噪声之间的差异以产生保护带值。

9. 发明申请

US20110252260A1 Reducing Power Requirements of a Multiple Core Processor 失效
标题翻译：降低多核处理器的电源要求
公开(公告)号：US20110252260A1
公开(公告)日：2011-10-13
申请号：US12756570
申请日：2010-04-08
申请人： Brian K. Flachs , Gilles Gervais , Sang H. Dhong , Tetsuji Tamura
发明人： Brian K. Flachs , Gilles Gervais , Sang H. Dhong , Tetsuji Tamura
IPC分类号： G06F1/00
CPC分类号： G06F9/5094 , G06F1/3287 , G06F1/329 , Y02D10/171 , Y02D10/22 , Y02D10/24 , Y02D50/20
摘要： A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable.
摘要翻译：提供了用于减少多核处理器消耗的功率的机制。响应于多个正常运行的处理器内核超过多核处理器中所需数量的处理器内核，功耗测量模块确定要禁用的正常运行的处理器内核的数量。功耗测量模块启动要由每个正常运行的处理器内核处理的相同数量的工作负载。功耗测量模块确定每个正常运行的处理器内核消耗的功耗。功耗测量模块取消激活具有最大功率的一个或多个正常运行的处理器内核，以使已正常运行的处理器内核的数量等于要禁用的正常运行的处理器内核的数量。

10. 发明授权

US07917347B2 Generating a worst case current waveform for testing of integrated circuit devices 有权
标题翻译：产生用于集成电路器件测试的最坏情况电流波形
公开(公告)号：US07917347B2
公开(公告)日：2011-03-29
申请号：US11927840
申请日：2007-10-30
申请人： Makoto Aikawa , Jonathan J. DeMent , Sang H. Dhong , Brian K. Flachs , Gilles Gervais , Iwao Takiguchi , Tetsuji Tamura
发明人： Makoto Aikawa , Jonathan J. DeMent , Sang H. Dhong , Brian K. Flachs , Gilles Gervais , Iwao Takiguchi , Tetsuji Tamura
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/318364
摘要： Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.
摘要翻译：提供了用于产生用于集成电路器件测试的最坏情况电流波形的机构。首先执行集成电路装置的结构分析，以确定要应用于集成电路装置的初始最坏情况功率工作负荷。此后，将得到的最坏情况功率工作量应用于模型，并且被模拟以产生输入到集成电路器件的电气模型以产生最坏情况噪声预算值的最坏情况电流波形。然后将最坏情况的噪声预算值与从最坏情况功率工作负载应用于硬件实现的集成电路设备的测量噪声进行比较。可以选择最坏情况下的电流波形以用于集成电路设备的未来测试，或者可以对仿真模型进行修改，并且基于比较的结果重复该过程。

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