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1. 发明申请

US20160212859A1 PRINTING ELECTRONIC CIRCUITRY 审中-公开
标题翻译：打印电子电路
公开(公告)号：US20160212859A1
公开(公告)日：2016-07-21
申请号：US14601285
申请日：2015-01-21
申请人： Gil Bellaiche , Aurel Faibis
发明人： Gil Bellaiche , Aurel Faibis
IPC分类号： H05K3/10
CPC分类号： H05K1/097 , B33Y80/00 , H05K3/0091 , H05K3/125 , H05K2201/0145 , H05K2201/026 , H05K2201/0323 , H05K2201/0326 , H05K2201/09245 , H05K2203/0759
摘要： A method of making a printed circuit board includes providing a substrate; providing a circuit design; determining non-conducting intersections between each of a plurality of conductive traces; forming a first set of conductive traces on the substrate; applying insulation material on the first set of traces at each of the non-conducting intersections; and forming a second set of conductive traces over the first set of traces and insulating material.
摘要翻译：制造印刷电路板的方法包括提供基板; 提供电路设计; 确定多个导电迹线中的每一个之间的非导通交点; 在所述衬底上形成第一组导电迹线; 在每个非导电交叉点处在第一组轨迹上施加绝缘材料; 以及在第一组迹线和绝缘材料上形成第二组导电迹线。

2. 发明申请

US20150296611A1 LOGIC GATE ARRAY 有权
标题翻译： LOGIC门阵列
公开(公告)号：US20150296611A1
公开(公告)日：2015-10-15
申请号：US14248378
申请日：2014-04-09
申请人： Gil Bellaiche
发明人： Gil Bellaiche
IPC分类号： H05K1/02 , H05K1/09
CPC分类号： H01L27/11803 , H01L21/76895 , H05K1/0289 , H05K1/092 , H05K3/4053 , H05K2203/173
摘要： A logic gate array includes a substrate; an array of first conductive lines with plurality of first gaps disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first gaps; an array of second conductive lines with plurality of second gaps disposed on each of the second conductive lines on the substrate wherein the array of first conductive lines is disposed in a second direction and wherein orientation of the second direction is oriented is different than the orientation of the first direction; and conductive ink dots printed on at least some of the intersection of the first conductive lines and the second conductive lines by connecting the corresponding first gaps and corresponding second gaps.
摘要翻译：逻辑门阵列包括衬底; 第一导电线阵列，其具有设置在所述基板上的每个所述第一导线上的多个第一间隙，其中所述第一导线阵列设置在第一方向上; 在第一导线上的隔离线阵列，其中隔离线不设置在第一间隙上; 第二导线的阵列，其具有设置在所述基板上的每个所述第二导线上的多个第二间隙，其中所述第一导线阵列沿第二方向设置，并且所述第二方向的定向取向不同于第一个方向并且通过连接相应的第一间隙和对应的第二间隙，印刷在第一导电线和第二导线之间的至少一些相交处的导电墨点。

3. 发明授权

US09265143B2 Logic gate array 有权
标题翻译：逻辑门阵列
公开(公告)号：US09265143B2
公开(公告)日：2016-02-16
申请号：US14248378
申请日：2014-04-09
申请人： Gil Bellaiche
发明人： Gil Bellaiche
IPC分类号： H01L25/00 , H05K1/02 , H05K1/09
CPC分类号： H01L27/11803 , H01L21/76895 , H05K1/0289 , H05K1/092 , H05K3/4053 , H05K2203/173
摘要： A logic gate array includes a substrate; an array of first conductive lines with plurality of first pads disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first pads; an array of second conductive lines with plurality of second pads disposed on each of the second conductive lines on the substrate wherein the array of first conductive lines is disposed in a second direction and wherein orientation of the second direction is oriented is different than the orientation of the first direction; and conductive ink dots printed on at least some of the intersection of the first conductive lines and the second conductive lines by connecting the corresponding first pads and corresponding second pads.
摘要翻译：逻辑门阵列包括衬底; 第一导电线阵列，其中多个第一焊盘设置在衬底上的每个第一导线上，其中第一导线阵列沿第一方向设置; 在所述第一导电线上方的隔离线阵列，其中所述隔离线未设置在所述第一焊盘上; 第二导线的阵列，其中多个第二焊盘设置在衬底上的每个第二导线上，其中第一导线阵列沿第二方向设置，并且其中第二方向的取向取向不同于第一个方向; 并且通过连接相应的第一焊盘和对应的第二焊盘，印刷在第一导电线和第二导电线的至少一些交叉点上的导电油墨点。

4. 发明授权

US09269723B2 Printing electronic circuitry logic 有权
标题翻译：打印电子电路逻辑
公开(公告)号：US09269723B2
公开(公告)日：2016-02-23
申请号：US14248374
申请日：2014-04-09
申请人： Gil Bellaiche
发明人： Gil Bellaiche
IPC分类号： H01L21/00 , H01L27/118 , H01L21/768
CPC分类号： H01L27/11803 , H01L21/76895 , H05K1/0289 , H05K1/092 , H05K3/4053 , H05K2203/173
摘要： A method of making a logic gate array includes providing a substrate; forming an array of first conductive lines with plurality of first pads disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; forming an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first pads; forming an array of second conductive lines with plurality of second pads disposed on each of the second conductive lines on the substrate wherein the array of second conductive lines is disposed in a second direction and wherein orientation of the second direction is different than the orientation of the first direction; and printing one or more conductive ink dots at least one intersection of the first conductive lines and the second conductive lines by connecting the corresponding first pads and corresponding second pads.
摘要翻译：制作逻辑门阵列的方法包括：提供衬底; 形成第一导电线阵列，其中多个第一焊盘设置在衬底上的每个第一导线上，其中第一导线阵列沿第一方向设置; 在所述第一导电线上形成隔离线阵列，其中所述隔离线不设置在所述第一焊盘上; 形成具有设置在所述基板上的每个所述第二导电线上的多个第二焊盘的第二导线阵列，其中所述第二导线阵列设置在第二方向上，并且所述第二方向的取向不同于第一方向以及通过连接相应的第一焊盘和相应的第二焊盘来将一个或多个导电油墨点印刷到第一导线和第二导线的至少一个交点。

5. 发明申请

US20150294982A1 PRINTING ELECTRONIC CIRCUITRY LOGIC 有权
标题翻译：打印电子电路逻辑
公开(公告)号：US20150294982A1
公开(公告)日：2015-10-15
申请号：US14248374
申请日：2014-04-09
申请人： Gil Bellaiche
发明人： Gil Bellaiche
IPC分类号： H01L27/118 , H01L21/768
CPC分类号： H01L27/11803 , H01L21/76895 , H05K1/0289 , H05K1/092 , H05K3/4053 , H05K2203/173
摘要： A method of making a logic gate array includes providing a substrate; forming an array of first conductive lines with plurality of first gaps disposed on each of the first conductive lines on the substrate wherein the array of first conductive lines is disposed in a first direction; forming an array of isolation lines over the first conductive lines wherein the isolation lines are not disposed on the first gaps; forming an array of second conductive lines with plurality of second gaps disposed on each of the second conductive lines on the substrate wherein the array of second conductive lines is disposed in a second direction and wherein orientation of the second direction is different than the orientation of the first direction; and printing one or more conductive ink dots at least one intersection of the first conductive lines and the second conductive lines by connecting the corresponding first gaps and corresponding second gaps.
摘要翻译：制作逻辑门阵列的方法包括：提供衬底; 形成具有设置在所述基板上的每个所述第一导线上的多个第一间隙的第一导线阵列，其中所述第一导线阵列沿第一方向设置; 在所述第一导线上形成隔离线阵列，其中所述隔离线不设置在所述第一间隙上; 形成具有设置在所述衬底上的每个所述第二导电线上的多个第二间隙的第二导电线阵列，其中所述第二导线阵列设置在第二方向上，并且所述第二方向的取向不同于所述第二导电线的取向第一方向以及通过连接相应的第一间隙和对应的第二间隙，将一个或多个导电油墨点印刷到第一导线和第二导线的至少一个交点。

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