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1. 发明授权

US4926323A Streamlined instruction processor 失效
标题翻译：精简指令处理器
公开(公告)号：US4926323A
公开(公告)日：1990-05-15
申请号：US163917
申请日：1988-03-03
申请人： Gigy Baror , Brian W. Case , Rod G. Fleck , Philip M. Freidin , Smeeta Gupta , William M. Johnson , Cheng-Gang Kong , Ole H. Moller , Timothy A. Olson , David I. Sorensen
发明人： Gigy Baror , Brian W. Case , Rod G. Fleck , Philip M. Freidin , Smeeta Gupta , William M. Johnson , Cheng-Gang Kong , Ole H. Moller , Timothy A. Olson , David I. Sorensen
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3867
摘要： A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles. The execution unit includes a storage facility, coupled to the data interface, for storing data in a file of data locations identified by file addresses. The storage facility includes at least two read ports and one write port operable in response to file addresses. An addressing unit coupled to receive the instructions from the instruction register, supplies the file addresses to the read ports and the write port under program control. In addition, the addressing unit is operable in response to a stack pointer providing dynamic allocation of the file of data locations to processes within the program.A memory management unit is coupled to the data interface. The memory management unit includes an address interface adapted for connection to the data memory and the instruction memory for supplying instruction addresses to the instruction memory and data addresses to the data memory, in a simple single access mode, a pipeline mode and a burst mode.
摘要翻译：精简指令处理器响应于由流水线循环中的预先指定组成的程序来处理数据。处理器包括指令提取单元，其包括适于连接到指令存储器并用于从指令存储器取出指令的指令接口。指令提取单元包括指令预取缓冲器，其耦合到指令接口，用于缓冲提供给指令接口的指令序列。分支目标高速缓冲存储器与预取缓冲器耦合，用于存储从指令存储器中的对应的一组位置检索的具有顺序指令地址的指令集。每个这样的集合中的第一条指令是程序中的分支目标指令。此外，包括适于连接到数据存储器的数据接口的执行单元在流水线循环中执行指令。执行单元包括耦合到数据接口的存储设备，用于将数据存储在由文件地址标识的数据位置的文件中。存储设备包括至少两个读端口和一个可响应文件地址操作的写端口。耦合以从指令寄存器接收指令的寻址单元，在程序控制下将文件地址提供给读端口和写端口。此外，寻址单元响应于堆栈指针提供动态分配数据位置文件到程序内的进程而可操作。存储器管理单元耦合到数据接口。存储器管理单元包括适于连接到数据存储器的地址接口和用于以简单的单次访问模式，流水线模式和突发模式向指令存储器提供指令地址和数据存储器的指令存储器。

2. 发明授权

US5317715A Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics 失效
标题翻译：减少的指令集计算机系统包括用于将高性能RISC接口耦合到具有不同性能特性的外围总线的装置和方法
公开(公告)号：US5317715A
公开(公告)日：1994-05-31
申请号：US911783
申请日：1992-07-10
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/40 , G06F13/00 , G06F13/23
CPC分类号： G06F13/4013 , G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.
摘要翻译：公开了用于向简化指令集计算机（RISC）系统的本地总线传输数据的方法和装置，包括至少一个中央处理器（“CPU”）的第一组高性能设备，和远程总线，第二组相对较低性能的设备以不限制RISC处理器性能的方式连接到该远程总线。根据本发明的优选实施例，公开了一种RISC架构，其包括新颖的数据传输控制器（“DTC”）或一组DTC，适用于在高性能本地总线与一个或多个本地总线之间执行上述数据传输功能通常具有不同（和较低）性能特征的完整子系统或外设的远程总线。由此产生的RISC节点允许商业化的外围设备和子系统与高性能RISC处理器配合使用，而不会限制RISC系统的性能。

3. 发明授权

US5142672A Data transfer controller incorporating direct memory access channels and address mapped input/output windows 失效
标题翻译：数据传输控制器包含直接存储器访问通道和地址映射输入/输出窗口
公开(公告)号：US5142672A
公开(公告)日：1992-08-25
申请号：US132296
申请日：1987-12-15
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

4. 发明授权

US4878166A Direct memory access apparatus and methods for transferring data between buses having different performance characteristics 失效
标题翻译：用于在具有不同性能特征的总线之间传送数据的直接存储器存取装置和方法
公开(公告)号：US4878166A
公开(公告)日：1989-10-31
申请号：US133094
申请日：1987-12-15
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The noval DMA may also be used as part of a data transfer controller (DTC) having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems and the like.

5. 发明申请

US20090125707A1 System and method for speculative global history prediction updating 有权
标题翻译：用于推测全球历史预测更新的系统和方法
公开(公告)号：US20090125707A1
公开(公告)日：2009-05-14
申请号：US11985025
申请日：2007-11-13
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

6. 发明申请

US20090198984A1 Global History Branch Prediction Updating Responsive to Taken Branches 有权
标题翻译：全球历史分支预测更新响应分支机构
公开(公告)号：US20090198984A1
公开(公告)日：2009-08-06
申请号：US12023303
申请日：2008-01-31
申请人： Jon A. Loschke , Timothy A. Olson , Terrence Matthew Potter
发明人： Jon A. Loschke , Timothy A. Olson , Terrence Matthew Potter
IPC分类号： G06F9/30
CPC分类号： G06F9/3848
摘要： A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的全局历史预测记录的系统和方法。在流水线微处理器执行过程的第一阶段，该方法接受连续操作的微处理器指令，包括具有关联分支地址的条件分支操作。利用分支地址访问和散列条件分支分辨率和预测的全局历史记录（GHR），创建第一个散列结果。第一个散列结果用于访问分支方向计数的索引分支历史表（BHT），BHT用于进行分支预测。如果分支预测被“取”，则将当前GHR值左移并用分支地址散列，创建用于创建更新的GHR的第二哈希结果。

7. 发明授权

US08833481B2 System for controlling wing tool bars of an agricultural implement having an angle sensor 有权
标题翻译：用于控制具有角度传感器的农具的机翼工具杆的系统
公开(公告)号：US08833481B2
公开(公告)日：2014-09-16
申请号：US13604752
申请日：2012-09-06
申请人： Timothy R. Blunier , Timothy A. Olson
发明人： Timothy R. Blunier , Timothy A. Olson
IPC分类号： A01B5/00 , A01B49/02
CPC分类号： A01B63/32 , A01B63/008 , A01B73/044
摘要： System for controlling wing tool bars of an agricultural implement are provided. One implement includes a tool bar assembly having a central tool bar and a first wing tool bar rotatably coupled to an end of the central tool bar. The implement also includes a first actuator coupled to the first wing tool bar and to the central tool bar, and configured to raise and lower the first wing tool bar. The implement includes a solenoid controlled valve fluidly coupled to the first actuator. The implement also includes a switch electrically coupled to the valve. The switch measures an angle of the first wing tool bar relative to the central tool bar and is configured to transition the valve between a first and a second position based on an angle of the first wing tool bar relative to the central tool bar.
摘要翻译：提供了一种用于控制农具的机翼工具条的系统。一个工具包括具有中心工具杆的工具杆组件和可旋转地联接到中心工具杆的端部的第一翼工具杆。该工具还包括耦合到第一翼工具杆和中心工具杆的第一致动器，并且构造成升高和降低第一翼工具杆。该工具包括流体地联接到第一致动器的电磁控制阀。该装置还包括电连接到阀的开关。开关测量第一翼形工具杆相对于中心工具杆的角度，并且构造成基于第一翼形工具杆相对于中心工具杆的角度在第一和第二位置之间转换阀。

8. 发明申请

US20100169627A1 System and method for repairing a speculative global history record 有权
标题翻译：用于修复投机性全球历史记录的系统和方法
公开(公告)号：US20100169627A1
公开(公告)日：2010-07-01
申请号：US12722220
申请日：2010-03-11
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

9. 发明授权

US07707398B2 System and method for speculative global history prediction updating 有权
标题翻译：用于推测全球历史预测更新的系统和方法
公开(公告)号：US07707398B2
公开(公告)日：2010-04-27
申请号：US11985025
申请日：2007-11-13
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

10. 发明授权

US07219326B2 Physical realization of dynamic logic using parameterized tile partitioning 有权
标题翻译：使用参数化瓦片分区实现动态逻辑
公开(公告)号：US07219326B2
公开(公告)日：2007-05-15
申请号：US10738278
申请日：2003-12-16
申请人： Jeffrey B. Reed , James S. Blomgren , Donald W. Glowka , Timothy A. Olson , Thomas W. Rudwick
发明人： Jeffrey B. Reed , James S. Blomgren , Donald W. Glowka , Timothy A. Olson , Thomas W. Rudwick
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.
摘要翻译：所公开的布局合成方法和设备的匹配算法在设计中定位晶体管模式匹配，将参数化的瓦片链接到每个识别的匹配，并且调整链接的参数化瓦片的某些可变参数以满足每个定位的匹配的物理设计要求。每个晶体管图案对应于参数化的瓦片，其是相应图案的实际物理表示，并且包括可变参数，其可以包括晶体管尺寸。匹配算法在设计中定位匹配的有序模式列表，每个匹配的名称，将正确的参数化图块链接到每个命名的匹配，并根据需要调整图块的变量参数。设计中的晶体管包含在唯一的一个命名匹配中。

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