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1. 发明申请

US20090125707A1 System and method for speculative global history prediction updating 有权
标题翻译：用于推测全球历史预测更新的系统和方法
公开(公告)号：US20090125707A1
公开(公告)日：2009-05-14
申请号：US11985025
申请日：2007-11-13
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

2. 发明申请

US20090198984A1 Global History Branch Prediction Updating Responsive to Taken Branches 有权
标题翻译：全球历史分支预测更新响应分支机构
公开(公告)号：US20090198984A1
公开(公告)日：2009-08-06
申请号：US12023303
申请日：2008-01-31
申请人： Jon A. Loschke , Timothy A. Olson , Terrence Matthew Potter
发明人： Jon A. Loschke , Timothy A. Olson , Terrence Matthew Potter
IPC分类号： G06F9/30
CPC分类号： G06F9/3848
摘要： A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的全局历史预测记录的系统和方法。在流水线微处理器执行过程的第一阶段，该方法接受连续操作的微处理器指令，包括具有关联分支地址的条件分支操作。利用分支地址访问和散列条件分支分辨率和预测的全局历史记录（GHR），创建第一个散列结果。第一个散列结果用于访问分支方向计数的索引分支历史表（BHT），BHT用于进行分支预测。如果分支预测被“取”，则将当前GHR值左移并用分支地址散列，创建用于创建更新的GHR的第二哈希结果。

3. 发明申请

US20100169627A1 System and method for repairing a speculative global history record 有权
标题翻译：用于修复投机性全球历史记录的系统和方法
公开(公告)号：US20100169627A1
公开(公告)日：2010-07-01
申请号：US12722220
申请日：2010-03-11
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

4. 发明授权

US07707398B2 System and method for speculative global history prediction updating 有权
标题翻译：用于推测全球历史预测更新的系统和方法
公开(公告)号：US07707398B2
公开(公告)日：2010-04-27
申请号：US11985025
申请日：2007-11-13
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

5. 发明授权

US07975133B1 Method for repairing a speculative global history record 有权
标题翻译：修复投机性全球历史记录的方法
公开(公告)号：US07975133B1
公开(公告)日：2011-07-05
申请号：US13016986
申请日：2011-01-29
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

6. 发明授权

US07904705B2 System and method for repairing a speculative global history record 有权
标题翻译：用于修复投机性全球历史记录的系统和方法
公开(公告)号：US07904705B2
公开(公告)日：2011-03-08
申请号：US12722220
申请日：2010-03-11
申请人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
发明人： Timothy A. Olson , Terrence Matthew Potter , Jon A. Loschke
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3863
摘要： A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的推测性全球历史预测记录的系统和方法。该方法接受具有连续操作的微处理器指令，包括具有关联的第一分支地址的条件分支操作。条件分支分辨率和预测的推测全球历史记录（SGHR）被访问并用第一个分支地址进行散列，创建第一个散列结果。第一个哈希结果用于对先前的第一分支分辨率的分支历史表（BHT）进行索引。结果，进行第一分支预测，并且用第一分支预测来更新SGHR。分支分辨率的非推测全局历史记录（NSGHR）用第一分支操作的分辨率更新，并且如果第一分支预测不正确，则使用NSGHR校正SGHR。

7. 发明授权

US07844806B2 Global history branch prediction updating responsive to taken branches 有权
标题翻译：全球历史分支预测更新响应采取分支
公开(公告)号：US07844806B2
公开(公告)日：2010-11-30
申请号：US12023303
申请日：2008-01-31
申请人： Jon A. Loschke , Timothy A. Olson , Terrence Matthew Potter
发明人： Jon A. Loschke , Timothy A. Olson , Terrence Matthew Potter
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR.
摘要翻译：提供一种用于使用流水线指令处理来更新微处理器系统中的全局历史预测记录的系统和方法。在流水线微处理器执行过程的第一阶段，该方法接受连续操作的微处理器指令，包括具有关联分支地址的条件分支操作。利用分支地址访问和散列条件分支分辨率和预测的全局历史记录（GHR），创建第一个散列结果。第一个散列结果用于访问分支方向计数的索引分支历史表（BHT），BHT用于进行分支预测。如果分支预测被“取”，则将当前GHR值左移并用分支地址散列，创建用于创建更新的GHR的第二哈希结果。

8. 发明授权

US09600288B1 Result bypass cache 有权
公开(公告)号：US09600288B1
公开(公告)日：2017-03-21
申请号：US13465372
申请日：2012-05-07
申请人： Terence M. Potter , Timothy A. Olson , James S. Blomgren , Robert A. Drebin , Douglas C. Youngwith , Jon A. Loschke
发明人： Terence M. Potter , Timothy A. Olson , James S. Blomgren , Robert A. Drebin , Douglas C. Youngwith , Jon A. Loschke
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F1/26 , G06F9/30047 , G06F9/30185 , G06F9/3824 , G06F9/3826 , G06F9/3832 , G06F9/3851 , G06F9/3887
摘要： A system and method for efficiently accessing operands in a datapath. An apparatus includes a data operand register file and an execution pipeline with multiple stages. In addition, the apparatus includes a result bypass cache configured to store data results conveyed by at least the final stage of the execution pipeline stage. Control logic is included which is configured to determine whether source operands for an instruction entering the pipeline are available in the last stage of the pipeline or in the result bypass cache. If the source operands are available in the last stage of the pipeline or the result bypass cache, they may be obtained from one of those locations rather than reading from the register file. If the source operands are not available from the last stage or the result bypass cache, then they may be obtained from the data operand register file.

9. 发明授权

US5317715A Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics 失效
标题翻译：减少的指令集计算机系统包括用于将高性能RISC接口耦合到具有不同性能特性的外围总线的装置和方法
公开(公告)号：US5317715A
公开(公告)日：1994-05-31
申请号：US911783
申请日：1992-07-10
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/40 , G06F13/00 , G06F13/23
CPC分类号： G06F13/4013 , G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.
摘要翻译：公开了用于向简化指令集计算机（RISC）系统的本地总线传输数据的方法和装置，包括至少一个中央处理器（“CPU”）的第一组高性能设备，和远程总线，第二组相对较低性能的设备以不限制RISC处理器性能的方式连接到该远程总线。根据本发明的优选实施例，公开了一种RISC架构，其包括新颖的数据传输控制器（“DTC”）或一组DTC，适用于在高性能本地总线与一个或多个本地总线之间执行上述数据传输功能通常具有不同（和较低）性能特征的完整子系统或外设的远程总线。由此产生的RISC节点允许商业化的外围设备和子系统与高性能RISC处理器配合使用，而不会限制RISC系统的性能。

10. 发明授权

US5142672A Data transfer controller incorporating direct memory access channels and address mapped input/output windows 失效
标题翻译：数据传输控制器包含直接存储器访问通道和地址映射输入/输出窗口
公开(公告)号：US5142672A
公开(公告)日：1992-08-25
申请号：US132296
申请日：1987-12-15
申请人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
发明人： William M. Johnson , Timothy A. Olson , Drew J. Dutton , Sherman Lee , David W. Stoenner
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

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