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1. 发明申请

US20100211757A1 Systolic Data Processing Apparatus and Method 有权
标题翻译：收缩数据处理装置及方法
公开(公告)号：US20100211757A1
公开(公告)日：2010-08-19
申请号：US12372469
申请日：2009-02-17
申请人： Gi-Ho Park , Shin-dug Kim , Jung-wook Park , Hoon-mo Yang , Sung-bae Park
发明人： Gi-Ho Park , Shin-dug Kim , Jung-wook Park , Hoon-mo Yang , Sung-bae Park
IPC分类号： G06F15/80 , G06F9/06 , G06F9/30
CPC分类号： G06F15/8007 , G06F15/8053
摘要： A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at each cycle for executing a program. The control unit inputs a new instruction to a first PE of the PE array at each cycle.
摘要翻译：收缩期数据处理装置包括处理元件（PE）阵列和控制单元。 PE阵列包括多个PE，每个PE根据输入指令执行相对于不同数据的线程，并在每个周期流水线执行程序。控制单元在每个周期向PE阵列的第一PE输入新的指令。

2. 发明授权

US08151090B2 Sequentially propagating instructions of thread through serially coupled PEs for concurrent processing respective thread on different data and synchronizing upon branch 有权
标题翻译：通过串行连接的PE顺序传播线程指令，用于并行处理不同数据上的各个线程，并在分支上同步
公开(公告)号：US08151090B2
公开(公告)日：2012-04-03
申请号：US12372469
申请日：2009-02-17
申请人： Gi-Ho Park , Shin-Dug Kim , Jung-Wook Park , Hoon-Mo Yang , Sung-Bae Park
发明人： Gi-Ho Park , Shin-Dug Kim , Jung-Wook Park , Hoon-Mo Yang , Sung-Bae Park
IPC分类号： G06F15/80
CPC分类号： G06F15/8007 , G06F15/8053
摘要： A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at each cycle for executing a program. The control unit inputs a new instruction to a first PE of the PE array at each cycle.
摘要翻译：收缩期数据处理装置包括处理元件（PE）阵列和控制单元。 PE阵列包括多个PE，每个PE根据输入指令执行相对于不同数据的线程，并在每个周期流水线执行程序。控制单元在每个周期向PE阵列的第一PE输入新的指令。

3. 发明授权

US07725641B2 Memory array structure and single instruction multiple data processor including the same and methods thereof 有权
标题翻译：内存阵列结构和单指令多数据处理器包括相同的方法
公开(公告)号：US07725641B2
公开(公告)日：2010-05-25
申请号：US11806593
申请日：2007-06-01
申请人： Gi-Ho Park , Shin-Dug Kim , Jung-Wook Park , Jun-Kyu Park , Sung-Bae Park
发明人： Gi-Ho Park , Shin-Dug Kim , Jung-Wook Park , Jun-Kyu Park , Sung-Bae Park
IPC分类号： G06F12/00
CPC分类号： G06F15/8015
摘要： A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder(codec) and configured to output a plurality of data from a plurality of banks of the memory in parallel. In addition, a data interconnection unit is configured to shift the plurality of data output from the memory and provide the shifted data to a plurality of operation units as input data. The operation result from each of the plurality of operation units is stored in a region of the memory.
摘要翻译：存储器可以被配置为重新排列和存储数据，以便为编码器 - 解码器（编解码器）所需的存储器访问模式实现无冲突模式，并被配置为并行地从存储器的多个存储体中输出多个数据。此外，数据互连单元被配置为移位从存储器输出的多个数据，并将移位的数据提供给多个操作单元作为输入数据。来自多个操作单元中的每一个的操作结果被存储在存储器的区域中。

4. 发明申请

US20080114921A1 Memory array structure and single instruction multiple data processor including the same and methods thereof 有权
标题翻译：内存阵列结构和单指令多数据处理器包括相同的方法
公开(公告)号：US20080114921A1
公开(公告)日：2008-05-15
申请号：US11806593
申请日：2007-06-01
申请人： Gi-Ho Park , Shin-Dug Kim , Jung-Wook Park , Jun-Kyu Park , Sung-Bae Park
发明人： Gi-Ho Park , Shin-Dug Kim , Jung-Wook Park , Jun-Kyu Park , Sung-Bae Park
IPC分类号： G06F12/00 , G06F15/80 , H04N11/02
CPC分类号： G06F15/8015
摘要： A memory may be configured to rearrange and store data to enable a conflict free mode for a memory access pattern required by a coder-decoder (codec).
摘要翻译：存储器可以被配置为重新排列和存储数据，以使得无冲突模式用于编码器 - 解码器（编解码器）所需的存储器访问模式。

5. 发明授权

US06272622B1 Method of and circuit for instruction/data prefetching using non-referenced prefetch cache 失效
标题翻译：使用非引用预取缓存的指令/数据预取方法和电路
公开(公告)号：US06272622B1
公开(公告)日：2001-08-07
申请号：US08522222
申请日：1995-09-01
申请人： Tack-Don Han , Gi-Ho Park , Shin-Dug Kim
发明人： Tack-Don Han , Gi-Ho Park , Shin-Dug Kim
IPC分类号： G06F900
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： A method of and a circuit for instruction/data prefetching using a non-referenced prefetch cache, adapted to store instruction/data blocks prefetched in accordance with a variety of existing prefetchinig machanisms, but not referenced by the central processing unit in an on-chip memory as the non-referenced prefetch cache without discarding them when they are replaced by new ones in a prefetch buffer so that a direct memory reference to the non-referenced prefetch instruction/data blocks can be achieved when they are to be referenced at later times, without any requirement of fetching or prefetching them from the lower memory again. Accordingly, it is possible to not only decrease the number of cache misses and the memory latency due to the fetching of instructions/data from the lower memory for the reference to the instructions/data, but also to reduce memory traffic.
摘要翻译：一种用于使用非参考预取高速缓存的指令/数据预取的方法和电路，其适于存储根据各种现有的预读取机制预取的指令/数据块，但不由片上的中央处理单元引用存储器作为非引用的预取缓存，而在预取缓冲器中被替换为新引用的预取缓存时，它们不会丢弃它们，以便在稍后引用时可以实现对非引用的预取指令/数据块的直接存储器引用，而不需要再次从下层存储器中取出或预取它们。因此，不仅可以减少高速缓存未命中的数量和由于从较低的存储器获取用于引用指令/数据的指令/数据引起的存储器等待时间，还可以减少存储器流量。

6. 发明申请

US20070192574A1 Branch target buffer, a branch prediction circuit and method thereof 审中-公开
标题翻译：分支目标缓冲器，分支预测电路及其方法
公开(公告)号：US20070192574A1
公开(公告)日：2007-08-16
申请号：US11700780
申请日：2007-02-01
申请人： Gi-Ho Park
发明人： Gi-Ho Park
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F1/32 , G06F9/3814
摘要： A branch target buffer, a branch prediction circuit and a method thereof are provided. The example branch target buffer may include a memory cell array storing a branch address and a target address, a decoder connected to the memory cell array through a word line, and providing a word line voltage to a selected word line in response to a fetch address, a sense amp connected to the memory cell array through a bit line and sensing and amplifying data of a selected memory cell and sense amp enable circuitry connected to the word line, the sense amp enable circuitry storing branch prediction information and controlling an operation of the sense amp based on the branch prediction information. The example method may be directed to a method of operating a branch target buffer, including determining whether an instruction to be executed by a processor is a branch instruction, determining, if the instruction is determined to be a branch instruction, whether the branch instruction is predicted to be taken and selectively buffering instructions, from one or more memory cells, associated with the branch instruction based on whether the branch instruction is predicted to be taken.
摘要翻译：提供了分支目标缓冲器，分支预测电路及其方法。示例性分支目标缓冲器可以包括存储分支地址和目标地址的存储单元阵列，通过字线连接到存储单元阵列的解码器，以及响应于提取地址向选定字线提供字线电压，通过位线连接到存储单元阵列的感测放大器，感测和放大所选存储单元的数据和连接到字线的感测放大器使能电路，读出放大器使能电路存储分支预测信息并控制基于分支预测信息的感测放大器。该示例方法可以涉及一种操作分支目标缓冲器的方法，包括确定由处理器执行的指令是否是分支指令，确定该指令是否为分支指令，分支指令是否为预测将基于是否预测分支指令被采取并选择性地缓冲与分支指令相关联的一个或多个存储器单元的指令。

7. 发明授权

US07623406B2 Accessing semiconductor memory device according to an address and additional access information 失效
标题翻译：根据地址和附加访问信息访问半导体存储器件
公开(公告)号：US07623406B2
公开(公告)日：2009-11-24
申请号：US11705485
申请日：2007-02-12
申请人： Gi-Ho Park , Gun-Ok Jung
发明人： Gi-Ho Park , Gun-Ok Jung
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C11/413 , G11C16/08
摘要： A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.
摘要翻译：半导体存储器件包括存储单元阵列，解码器和访问控制单元。解码器根据存储单元阵列中的多个存储单元的地址产生字线电压。访问控制单元根据字线电压和与该地址分离的附加访问信息控制对多个存储器单元的访问。

8. 发明授权

US5935299A Apparatus and method of spray dryer/bag filter using circulating shield air 失效
标题翻译：使用循环屏蔽空气的喷雾干燥器/袋式过滤器的装置和方法
公开(公告)号：US5935299A
公开(公告)日：1999-08-10
申请号：US923888
申请日：1997-09-04
申请人： Chil-Lim Park , Eui Sin Lee , Byung-Hwan Kim , Gi-Ho Park , Hee Jin In
发明人： Chil-Lim Park , Eui Sin Lee , Byung-Hwan Kim , Gi-Ho Park , Hee Jin In
IPC分类号： B01D53/34 , B01D47/06 , B01D53/40 , B01F3/04
CPC分类号： B01D47/06 , B01D53/40 , Y10S261/27
摘要： A spray dryer/bag filter apparatus for removing flue gas from an incinerator, which is structurized to re-circulate the purified gas as the shield air for protecting the slurry spraying nozzle thermally from hot gas without using any additional blower to introduce external air, that the flue gas is not diluted.
摘要翻译：一种用于从焚化炉除去烟道气的喷雾干燥器/袋式过滤装置，其被结构化以使作为屏蔽空气的纯化气体再循环，用于保护浆料喷射喷嘴免受热气体的热量而不使用任何额外的鼓风机引入外部空气，烟气不被稀释。

9. 发明授权

US07227791B2 Semiconductor memory device including circuit to store access data 有权
标题翻译：半导体存储器件包括存储访问数据的电路
公开(公告)号：US07227791B2
公开(公告)日：2007-06-05
申请号：US11181144
申请日：2005-07-13
申请人： Gi-Ho Park
发明人： Gi-Ho Park
IPC分类号： G11C7/10
CPC分类号： G11C8/08 , G11C5/14
摘要： We describe a semiconductor memory device including a memory cell array and a storage device to store access data. The memory cell array is accessed responsive to the access data. The memory cell array access is determined by the access data stored in the storage device. The memory cell array is accessed according to access data only if necessary, drastically reducing power dissipation.
摘要翻译：我们描述一种包括存储单元阵列的半导体存储器件和用于存储访问数据的存储设备。响应于访问数据访问存储单元阵列。存储单元阵列访问由存储在存储设备中的访问数据确定。只有在必要时才根据访问数据访问存储单元阵列，从而大大降低功耗。

10. 发明申请

US20070195598A1 Accessing semiconductor memory device according to an address and additional access information 失效
标题翻译：根据地址和附加访问信息访问半导体存储器件
公开(公告)号：US20070195598A1
公开(公告)日：2007-08-23
申请号：US11705485
申请日：2007-02-12
申请人： Gi-Ho Park , Gun-Ok Jung
发明人： Gi-Ho Park , Gun-Ok Jung
IPC分类号： G11C16/04 , G11C5/14 , G11C8/00 , G11C11/34 , G11C7/02
CPC分类号： G11C8/10 , G11C11/413 , G11C16/08
摘要： A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.
摘要翻译：半导体存储器件包括存储单元阵列，解码器和访问控制单元。解码器根据存储单元阵列中的多个存储单元的地址产生字线电压。访问控制单元根据字线电压和与该地址分离的附加访问信息控制对多个存储器单元的访问。

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