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1. 发明授权

US07205395B2 Process of preparing azithromycin and crystalline 9-deoxo-9a-aza-9a-homoerythromycin A hydrate used therein 失效
标题翻译：制备阿奇霉素和结晶9-脱氧-9a-氮杂-9a-高红霉素A水合物的方法
公开(公告)号：US07205395B2
公开(公告)日：2007-04-17
申请号：US10509934
申请日：2002-04-03
申请人： Gi Jeong Kim , Mi Ra Seong , Sang Min Yun , Kwee Hyun Suh
发明人： Gi Jeong Kim , Mi Ra Seong , Sang Min Yun , Kwee Hyun Suh
IPC分类号： C07H17/08
CPC分类号： C07H17/08 , C07H17/00
摘要： Azithromycin is prepared in a high yield by a simple process using a crystalline 9-deoxo-9a-aza-9a-homoerythromycin A hydrate.
摘要翻译：通过使用结晶9-脱氧-9a-氮杂-9a-高红霉素A水合物的简单方法以高产率制备阿奇霉素。

2. 发明授权

US09472494B2 Lead frame for semiconductor device 有权
标题翻译：半导体器件引线框架
公开(公告)号：US09472494B2
公开(公告)日：2016-10-18
申请号：US13466717
申请日：2012-05-08
申请人： Joon Su Kim , Jung Soo Park , Gi Jeong Kim
发明人： Joon Su Kim , Jung Soo Park , Gi Jeong Kim
IPC分类号： H01L23/48 , H01L23/495
CPC分类号： H01L23/49582 , H01L2924/0002 , H01L2924/00
摘要： Provided is a lead frame for a semiconductor device, which includes a base layer made of copper, a strike plating layer or a self assembly monolayer (SAM), thereby preventing oxidation of a base layer while simplifying the manufacturing process, reducing the manufacturing costs and reducing a failure ratio. In one embodiment, in the lead frame for a semiconductor device including a die pad and a plurality of leads positioned adjacent to each other around the die pad, the lead frame includes a base layer made of copper; and a first strike plating layer formed on the one or more portions of the surface of the base layer.
摘要翻译：提供一种半导体器件的引线框架，其包括由铜制成的基底层，触击镀层或自组装单层（SAM），从而防止了基底层的氧化，同时简化了制造工艺，降低了制造成本和降低故障率。在一个实施例中，在用于半导体器件的引线框架中，引线框架包括由铜制成的基极层，所述引线框架包括管芯焊盘和围绕管芯焊盘彼此相邻定位的多个引线，以及形成在所述基底层的所述表面的所述一个或多个部分上的第一触击镀层。

3. 发明授权

US08674485B1 Semiconductor device including leadframe with downsets 有权
标题翻译：半导体器件包括带底片的引线框架
公开(公告)号：US08674485B1
公开(公告)日：2014-03-18
申请号：US12963431
申请日：2010-12-08
申请人： Gi Jeong Kim , Jae Yoon Kim , Kyu Won Lee
发明人： Gi Jeong Kim , Jae Yoon Kim , Kyu Won Lee
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/49541 , H01L23/49551 , H01L23/49558 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： In one embodiment, a semiconductor package includes a generally planar die paddle or die pad that defines multiple peripheral edge segments, and includes one or more tie bars protruding therefrom. In addition, the semiconductor package includes a plurality of leads, portions of which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body. The one or more tie bars and the plurality of leads include downsets that are sized and oriented relative to each other to facilitate enhanced manufacturing.
摘要翻译：在一个实施例中，半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘，并且包括从其突出的一个或多个连接杆。此外，半导体封装包括多个引线，其多个引线从半导体封装的封装主体的相应侧表面突出。连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。芯片焊盘，引线和半导体管芯的至少一部分被封装体封装。一个或多个连接杆和多个引线包括相对于彼此定尺寸和定向的下沉，以有助于增强制造。

4. 发明授权

US08184453B1 Increased capacity semiconductor package 有权
标题翻译：增加容量的半导体封装
公开(公告)号：US08184453B1
公开(公告)日：2012-05-22
申请号：US12183979
申请日：2008-07-31
申请人： Jae Yoon Kim , Gi Jeong Kim , Myung Soo Moon
发明人： Jae Yoon Kim , Gi Jeong Kim , Myung Soo Moon
IPC分类号： H05K5/02
CPC分类号： H01L23/49541 , H01L21/4828 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L2224/32245 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01079 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Disclosed is a lead frame and a semiconductor device including the same. The lead frame is provided with a die pad, and first, second and third lands sequentially arranged on an outer circumferential edge. The lead frame can separate the first and second lands or the die pad and the first land using a plating layer formed on the lead frame as a mask, instead of using a separate mask by etching after the application of the encapsulant. As a result thereof, a plurality of lands can be formed at low cost, in comparison with a conventional method. Additionally, the first, second and third lands are exposed to the outside through a lower portion of an encapsulant, and can be surface mounted on an external device through the first, second and third lands. A plating layer formed on bottom surfaces of the first, second and third lands of the lead frame and a process for separately plating nickel (Ni)/gold (An), Ni/Pd/Au, or tin (Sn) can be omitted so as to easily surface mount the semiconductor device to the external device.
摘要翻译：公开了一种引线框架和包括该引线框架的半导体器件。引线框架设置有管芯焊盘，并且顺序地布置在外周边缘上的第一，第二和第三焊盘。引线框架可以使用形成在引线框架上的镀层作为掩模来分离第一和第二焊盘或裸片焊盘和第一焊盘，而不是在施加密封剂之后通过蚀刻来使用单独的掩模。作为其结果，与传统方法相比，可以以低成本形成多个焊盘。此外，第一，第二和第三焊盘通过密封剂的下部暴露于外部，并且可以通过第一，第二和第三焊盘表面安装在外部设备上。形成在引线框架的第一，第二和第三焊盘的底面上的镀层以及分别镀镍（Ni）/金（An），Ni / Pd / Au或锡（Sn）的工艺可以省略以便容易地将半导体器件表面安装到外部设备。

5. 发明授权

US08823152B1 Semiconductor device with increased I/O leadframe 有权
标题翻译：具有增加的I / O引线框的半导体器件
公开(公告)号：US08823152B1
公开(公告)日：2014-09-02
申请号：US13181248
申请日：2011-07-12
申请人： Gi Jeong Kim , Wan Jong Kim
发明人： Gi Jeong Kim , Wan Jong Kim
IPC分类号： H01L23/495
CPC分类号： H01L23/49551 , H01L23/3107 , H01L23/3128 , H01L23/49541 , H01L23/49548 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2224/73265 , H01L2224/92247 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10162 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a semiconductor package (e.g., a QFP package) includes a leadframe sized and configured to increase the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions that are provided in at least one row or ring, which at least partially circumvents the die pad, with other leads including portions that protrude from respective side surfaces of a package body of the semiconductor package. At least one semiconductor die is connected to the top surface of the die pad and is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by a package body, with at least portions of the bottom surfaces of the die pad and some of the leads being exposed in a common exterior surface of the package body.
摘要翻译：在一个实施例中，半导体封装（例如，QFP封装）包括引线框架，其大小和配置以增加半导体封装中的暴露引线的可用数量。更具体地，半导体封装包括限定多个外围边缘段的大致平面的管芯焊盘。此外，半导体封装包括多个引线。这些引线中的一些包括设置在至少一行或多个环中的暴露的底表面部分，其至少部分地绕开管芯焊盘，其它引线包括从半导体封装的封装主体的相应侧表面突出的部分。至少一个半导体管芯连接到管芯焊盘的顶表面，并且电连接到至少一些引线。芯片焊盘，引线和半导体管芯的至少一部分被封装主体封装，其中芯片焊盘的底表面的至少部分和一些引线暴露在封装主体的公共外表面中。

6. 发明申请

US20120299172A1 LEAD FRAME FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件引线框架
公开(公告)号：US20120299172A1
公开(公告)日：2012-11-29
申请号：US13466717
申请日：2012-05-08
申请人： Joon Su Kim , Jung Soo Park , Gi Jeong Kim
发明人： Joon Su Kim , Jung Soo Park , Gi Jeong Kim
IPC分类号： H01L23/495 , H01L21/28
CPC分类号： H01L23/49582 , H01L2924/0002 , H01L2924/00
摘要： Provided is a lead frame for a semiconductor device, which includes a base layer made of copper, a strike plating layer or a self assembly monolayer (SAM), thereby preventing oxidation of a base layer while simplifying the manufacturing process, reducing the manufacturing costs and reducing a failure ratio. In one embodiment, in the lead frame for a semiconductor device including a die pad and a plurality of leads positioned adjacent to each other around the die pad, the lead frame includes a base layer made of copper; and a first strike plating layer formed on the one or more portions of the surface of the base layer.
摘要翻译：提供一种半导体器件的引线框架，其包括由铜制成的基底层，触击镀层或自组装单层（SAM），从而防止了基底层的氧化，同时简化了制造工艺，降低了制造成本和降低故障率。在一个实施例中，在用于半导体器件的引线框架中，引线框架包括由铜制成的基极层，所述引线框架包括管芯焊盘和围绕管芯焊盘彼此相邻定位的多个引线，以及形成在所述基底层的所述表面的所述一个或多个部分上的第一触击镀层。

7. 发明授权

US08188579B1 Semiconductor device including leadframe having power bars and increased I/O 有权
标题翻译：半导体器件包括具有功率条的引线框和增加的I / O
公开(公告)号：US08188579B1
公开(公告)日：2012-05-29
申请号：US12965582
申请日：2010-12-10
申请人： Gi Jeong Kim , Yeon Ho Choi
发明人： Gi Jeong Kim , Yeon Ho Choi
IPC分类号： H01L23/495
CPC分类号： H01L23/49551 , H01L23/3107 , H01L23/49503 , H01L23/49541 , H01L23/49544 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include bottom surface portions which, in the completed semiconductor package, are exposed and at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body in the completed semiconductor package. The semiconductor package also includes one or more power bars and/or one or more ground rings which are integral portions of the original leadframe used to fabricate the same.
摘要翻译：根据本发明，提供了包括唯一配置的引线框的半导体封装（例如，QFP封装），其尺寸和配置为使半导体封装中的暴露引线的可用数量最大化。更具体地，半导体封装包括限定多个外围边缘段的大致平面的管芯焊盘或管芯焊盘。此外，半导体封装包括多个引线。这些引线中的一些包括底表面部分，其在完成的半导体封装中被暴露并且至少部分地绕开管芯焊盘，其它引线包括从完成的半导体封装中的封装体的相应侧表面突出的部分。半导体封装还包括一个或多个电源条和/或一个或多个接地环，它们是用于制造原始引线框的整体部分。

8. 发明授权

US07875963B1 Semiconductor device including leadframe having power bars and increased I/O 有权
标题翻译：半导体器件包括具有功率条的引线框和增加的I / O
公开(公告)号：US07875963B1
公开(公告)日：2011-01-25
申请号：US12276121
申请日：2008-11-21
申请人： Gi Jeong Kim , Yeon Ho Choi
发明人： Gi Jeong Kim , Yeon Ho Choi
IPC分类号： H01L23/495
CPC分类号： H01L23/49551 , H01L23/3107 , H01L23/49503 , H01L23/49541 , H01L23/49544 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/49171 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include bottom surface portions which, in the completed semiconductor package, are exposed and at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body in the completed semiconductor package. The semiconductor package also includes one or more power bars and/or one or more ground rings which are integral portions of the original leadframe used to fabricate the same.
摘要翻译：根据本发明，提供了包括唯一配置的引线框的半导体封装（例如，QFP封装），其尺寸和配置为使半导体封装中的暴露引线的可用数量最大化。更具体地，半导体封装包括限定多个外围边缘段的大致平面的管芯焊盘或管芯焊盘。此外，半导体封装包括多个引线。这些引线中的一些包括底表面部分，其在完成的半导体封装中被暴露并且至少部分地绕开管芯焊盘，其它引线包括从完成的半导体封装中的封装体的相应侧表面突出的部分。半导体封装还包括一个或多个电源条和/或一个或多个接地环，它们是用于制造原始引线框的整体部分。

9. 发明申请

US20100099896A1 METHOD OF PREPARING DOCETAXEL AND INTERMEDIATES USED THEREIN 审中-公开
标题翻译：制备DOCETAXEL的方法及其使用的中间体
公开(公告)号：US20100099896A1
公开(公告)日：2010-04-22
申请号：US12517623
申请日：2007-12-03
申请人： Nam Du Kim , Wooseob Shin , Jaehyuk Jung , Dong Jun KIm , Gi Jeong Kim , Young Ho Moon , Young-Kil Chang , Gwan Sun Lee
发明人： Nam Du Kim , Wooseob Shin , Jaehyuk Jung , Dong Jun KIm , Gi Jeong Kim , Young Ho Moon , Young-Kil Chang , Gwan Sun Lee
IPC分类号： C07D305/14
CPC分类号： C07D305/14 , C07D263/04 , Y02P20/55
摘要： The present invention relates to a novel method for preparing docetaxel having anti-tumor and anti-leukemia activity, and intermediates useful for preparing docetaxel.
摘要翻译：本发明涉及一种制备具有抗肿瘤和抗白血病活性的多西紫杉醇的新方法，以及可用于制备多西紫杉醇的中间体。

10. 发明授权

US07091594B1 Leadframe type semiconductor package having reduced inductance and its manufacturing method 有权
标题翻译：具有降低的电感的引线框式半导体封装及其制造方法
公开(公告)号：US07091594B1
公开(公告)日：2006-08-15
申请号：US10766046
申请日：2004-01-28
申请人： Gi Jeong Kim , Jin Han Kim , Jin Seok Oh
发明人： Gi Jeong Kim , Jin Han Kim , Jin Seok Oh
IPC分类号： H01L23/22
CPC分类号： H01L23/4334 , H01L23/49541 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/4911 , H01L2224/73265 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor die comprising a heat sink having opposed top and bottom surfaces and defining a peripheral edge. Attached to the top surface of the heat sink is a semiconductor die. Extending at least partially about the semiconductor die is a plurality of leads, at least some of which are electrically connected to the semiconductor die. Attached to the top surface of the heat sink between the semiconductor die and the peripheral edge thereof is at least one first ground lead. Also attached to the top surface of the heat sink and protruding beyond the peripheral edge thereof is at least one second ground lead. A plurality of ground wires conductively connect the semiconductor die, the first and second ground leads and the heat sink to each other. A package body at least partially encapsulates the heat sink, the semiconductor die, the leads, the first and second ground leads, and the ground wires such that at least portions of the second ground leads and the leads protrude from the package body.
摘要翻译：一种半导体管芯，包括具有相对的顶表面和底表面并限定外围边缘的散热器。连接到散热器的顶表面是半导体管芯。至少部分地围绕半导体管芯延伸的是多个引线，其中至少一些引线电连接到半导体管芯。连接到半导体管芯和其周边边缘之间的散热器的顶表面是至少一个第一接地引线。还附接到散热器的顶表面并突出超过其周边的至少一个第二接地引线。多个接地线将半导体管芯，第一和第二接地引线和散热器彼此导电连接。封装体至少部分地封装散热器，半导体管芯，引线，第一和第二接地引线以及接地线，使得第二接地引线和引线的至少一部分从封装主体突出。

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