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1. 发明申请

US20110090665A1 THIN FILM SURFACE MOUNT COMPONENTS 有权
标题翻译：薄膜表面安装组件
公开(公告)号：US20110090665A1
公开(公告)日：2011-04-21
申请号：US12904315
申请日：2010-10-14
申请人： Gheorghe Korony , Andrew P. Ritter
发明人： Gheorghe Korony , Andrew P. Ritter
IPC分类号： H05K7/00 , H05K3/00
CPC分类号： H03H7/17 , H01C1/148 , H01C7/006 , H01F5/003 , H01F27/2804 , H01F2027/2809 , H01G4/224 , H01G4/248 , H01G4/33 , H01L2924/0002 , H03H7/0115 , H03H2001/0085 , H05K1/111 , H05K1/186 , H05K3/4611 , H05K3/467 , H05K3/4697 , Y10T29/49124 , H01L2924/00
摘要： Surface mount components and related methods of manufacture involve one or more thin film circuits provided between first and second insulating substrates. The thin film circuits may include one or more passive components, including resistors, capacitors, inductors, arrays of one or more passive components, networks or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with internal conductive pads being exposed between the substrates on end and/or side surfaces of the surface mount component. The exposed conductive pads are then electrically connected to external terminations. The external terminations may include a variety of different materials, including at least one layer of conductive polymer and may be formed as termination stripes, end caps or the like. Optional shield layers may also be provided on top and/or bottom device surfaces to protect the surface mount components from signal interference. For embodiments where one or more thin film circuits are provided between insulating base and cover substrates, such thin film circuit(s) can be formed with conductive pads that extend to and are initially exposed along one or more surfaces of the resultant component. The cover substrate is formed with a plurality of conductive elements (e.g., internal active electrodes, internal anchor electrodes and/or external anchor electrodes) that are designed to generally align with the conductive pads formed on the base substrate such that conductive element portions are exposed in groups along one or more peripheral surfaces of a device. External plated terminations are then formed directly to the exposed portions of the conductive elements.
摘要翻译：表面安装部件和相关的制造方法涉及设置在第一和第二绝缘基板之间的一个或多个薄膜电路。薄膜电路可以包括一个或多个无源组件，包括电阻器，电容器，电感器，一个或多个无源组件的阵列，多个无源组件的网络或滤波器。这样的薄膜电路可以夹在第一和第二绝缘基板之间，其中内部导电焊盘暴露在表面安装部件的端部和/或侧表面之间的基板之间。暴露的导电焊盘然后电连接到外部端接。外部终端可以包括各种不同的材料，包括至少一层导电聚合物，并且可以形成为端接条，端盖等。也可以在顶部和/或底部设备表面上设置可选屏蔽层，以保护表面安装部件免受信号干扰。对于在绝缘基底和覆盖基底之间提供一个或多个薄膜电路的实施例，这样的薄膜电路可以形成有导电垫，其延伸到并最初沿所得部件的一个或多个表面暴露。覆盖基板形成有多个导电元件（例如，内部有源电极，内部锚定电极和/或外部锚定电极），其被设计成与形成在基底基板上的导电焊盘大致对准，使得导电元件部分暴露沿着设备的一个或多个外围表面组合。然后将外部电镀端接件直接形成到导电元件的暴露部分。

2. 发明授权

US09450556B2 Thin film surface mount components 有权
标题翻译：薄膜表面贴装元件
公开(公告)号：US09450556B2
公开(公告)日：2016-09-20
申请号：US12904315
申请日：2010-10-14
申请人： Gheorghe Korony , Andrew P. Ritter
发明人： Gheorghe Korony , Andrew P. Ritter
IPC分类号： H05K7/00 , H01G5/00 , H03H7/01 , H01C1/148 , H01C7/00 , H01F5/00 , H01G4/224 , H01G4/248 , H01G4/33 , H03H1/00
CPC分类号： H03H7/17 , H01C1/148 , H01C7/006 , H01F5/003 , H01F27/2804 , H01F2027/2809 , H01G4/224 , H01G4/248 , H01G4/33 , H01L2924/0002 , H03H7/0115 , H03H2001/0085 , H05K1/111 , H05K1/186 , H05K3/4611 , H05K3/467 , H05K3/4697 , Y10T29/49124 , H01L2924/00
摘要： Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components. Such thin film circuit(s) can be sandwiched between first and second insulating substrates with internal conductive pads which are exposed to the outside of the surface mount component and electrically connected to external terminations. External terminations may include at least one layer of conductive polymer. Optional shield layers may protect the surface mount components from signal interference. A cover substrate may be formed with a plurality of conductive elements that are designed to generally align with the conductive pads such that conductive element portions are exposed in groups along surfaces of a device.
摘要翻译：表面贴装元件及相关方法涉及第一和第二绝缘基板之间的薄膜电路。薄膜电路可以包括无源组件，包括电阻器，电容器，电感器，这种组件的阵列，网络或多个无源组件的滤波器。这样的薄膜电路可以被夹在具有暴露于表面安装部件的外部并且电连接到外部端子的内部导电焊盘的第一和第二绝缘基板之间。外部终端可以包括至少一层导电聚合物。可选的屏蔽层可以保护表面贴装元件免受信号干扰。覆盖衬底可以形成有多个导电元件，其被设计为与导电焊盘大体对准，使得导电元件部分沿着器件的表面以组的形式暴露。

3. 发明授权

US08446705B2 Ultra broadband capacitor 有权
标题翻译：超宽带电容
公开(公告)号：US08446705B2
公开(公告)日：2013-05-21
申请号：US12538584
申请日：2009-08-10
申请人： Andrew P. Ritter , John L. Galvagni , John Mruz , Robert Grossbach , Marianne Berolini
发明人： Andrew P. Ritter , John L. Galvagni , John Mruz , Robert Grossbach , Marianne Berolini
IPC分类号： H01G4/30 , H01G4/06 , H01G4/005 , H01G4/228
CPC分类号： H01G4/012 , H01G4/005 , H01G4/30 , Y10T29/435
摘要： Disclosed are apparatus and methodology for inexpensive realization of one or more secondary capacitors within a monolithic body that already includes a first, larger capacitor to provide ultra wideband structures. Alternating layers of electrodes are provided with arm portions that embrace portions of adjacent electrode layers so as to create additional coupling effects within the capacitor structure thereby producing multiple additional equivalent capacitor structures within the device.
摘要翻译：公开了用于便宜地实现单块体内的一个或多个二次电容器的装置和方法，其已经包括第一较大电容器以提供超宽带结构。电极的交替层设置有包围相邻电极层的部分的臂部分，以便在电容器结构内产生额外的耦合效应，从而在器件内产生多个额外的等效电容器结构。

4. 发明授权

US07697262B2 Multilayer ceramic capacitor with internal current cancellation and bottom terminals 有权
标题翻译：具有内部电流消除和底部端子的多层陶瓷电容器
公开(公告)号：US07697262B2
公开(公告)日：2010-04-13
申请号：US12193498
申请日：2008-08-18
申请人： Andrew P. Ritter , John L. Galvagni
发明人： Andrew P. Ritter , John L. Galvagni
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01C1/148 , H01C7/18 , H01G2/065 , H01G4/012 , H01G4/30 , H05K1/0231 , H05K1/113 , H05K2201/0792 , Y10T29/435
摘要： Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.
摘要翻译：低电感电容器包括布置在电介质层之间并定向为使得电极基本上垂直于安装表面的电极。垂直电极沿着器件外围露出，以确定在哪里形成终端焊盘，限定了焊盘之间的狭窄和可控的间距，用于减小电流环路面积，从而降低了元件电感。可以通过叉指式终端来提供电流回路面积和部件等效串联电感（ESL）的进一步减小。端接可以通过各种无电镀技术形成，并且可以直接焊接到电路板焊盘。端子也可以位于电容器的“端部”上，以实现电气测试或控制焊接圆角尺寸和形状。可以在设备的给定底部（安装）表面上形成两端子器件以及具有多个端子的器件。端子也可以形成在顶表面（与指定的安装表面相对）上，并且可以是镜像，反向镜像或相对于底表面的不同形状。

5. 发明授权

US06960366B2 Plated terminations 有权
公开(公告)号：US06960366B2
公开(公告)日：2005-11-01
申请号：US10632514
申请日：2003-08-01
申请人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , Sriram Dattaguru
发明人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , Sriram Dattaguru
IPC分类号： H01G4/252 , B05D5/12 , C23C18/16 , H01C1/142 , H01F5/00 , H01F27/29 , H01G2/06 , H01G4/12 , H01G4/228 , H01G4/232 , H01G4/30 , H01G4/38 , H01G7/00 , H01L21/60 , H01L23/50 , H05K1/09 , H05K1/11 , H05K3/40
CPC分类号： H01C1/14 , C23C18/1605 , C23C18/1639 , C23C18/1886 , H01C7/008 , H01C7/10 , H01G4/005 , H01G4/232 , H01G4/30 , H05K1/181 , Y02P70/611 , Y10T29/43 , Y10T29/435
摘要： Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on one or both of top and bottom surfaces of a monolithic structure can facilitate the formation of selective wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

6. 发明授权

US06525628B1 Surface mount RC array with narrow tab portions on each of the electrode plates 失效
标题翻译：在每个电极板上具有窄突片部分的表面安装RC阵列
公开(公告)号：US06525628B1
公开(公告)日：2003-02-25
申请号：US09335991
申请日：1999-06-18
申请人： Andrew P. Ritter , Andrew Blair , Maureen Strawhorne , Clare Ashley Moore , Robert H. Heistand, II
发明人： Andrew P. Ritter , Andrew Blair , Maureen Strawhorne , Clare Ashley Moore , Robert H. Heistand, II
IPC分类号： H03H102
CPC分类号： H01G4/40 , H01C13/02 , H03H1/02 , H03H2001/0085 , H05K3/3442
摘要： Both discrete and array RC components are described using cofireable resistive material as part of internal electrodes of the device. The devices include a sintered body of multilayer ceramic material in which multiple first and second electrode layers are stacked. Each of the first layers comprises at least one resistive electrode pattern extending across the sintered body between respective pairs of terminations. The second layers comprise an electrode pattern extending transverse to the resistive electrode pattern, such as between end terminations. In some embodiments, opposing side electrodes serve as input and output terminals of a respective feedthrough filter. In a feedthrough arrangement, the third terminal may be provided by one or both of the end terminals. The invention also describes an improved termination structure including a layer made from a metal oxide material.
摘要翻译：使用可共同电阻材料作为器件的内部电极的一部分来描述分立和阵列RC组件。这些器件包括堆叠多个第一和第二电极层的多层陶瓷材料的烧结体。每个第一层包括在相应的终端对之间延伸穿过烧结体的至少一个电阻电极图案。第二层包括横向于电阻电极图案延伸的电极图案，例如终端之间。在一些实施例中，相对的侧电极用作相应的馈通过滤器的输入和输出端子。在馈通装置中，第三端子可以由一个端子端子或两个端子端子提供。本发明还描述了一种改进的端接结构，其包括由金属氧化物材料制成的层。

7. 发明授权

US5880925A Surface mount multilayer capacitor 失效
标题翻译：表面贴装多层电容器
公开(公告)号：US5880925A
公开(公告)日：1999-03-09
申请号：US884597
申请日：1997-06-27
申请人： David A. DuPre , John L. Galvagni , Andrew P. Ritter
发明人： David A. DuPre , John L. Galvagni , Andrew P. Ritter
IPC分类号： H01G4/12 , H01G2/06 , H01G4/252 , H01G4/30 , H05K1/02 , H05K1/11 , H05K1/18 , H05K3/34 , H01G4/005 , H01G4/06 , H01G4/228
CPC分类号： H01G2/065 , H01G4/30 , H05K3/3442 , H05K1/0216 , H05K1/0231 , H05K1/112 , H05K2201/09381 , H05K2201/09663 , H05K2201/0979 , H05K2201/10045 , H05K2201/10636 , Y02P70/611 , Y02P70/613
摘要： A multilayer ceramic device suitable for use in surface mount decoupling applications may have a single capacitor or a capacitor array. The device has a capacitor body defining a plurality of electrical terminals on an outer surface thereof. The terminals are interdigitated such that a respective first polarity terminal will be adjacent to a respective second polarity terminal (and vice versa). The capacitor body contains a plurality of interleaved capacitor plates in opposed and spaced apart relation. Capacitor plates of the first polarity are electrically connected to respective first polarity terminals via a plurality of lead structures. Likewise, a plurality of lead structures electrically connect capacitor plates of the second polarity to respective second polarity terminals.
摘要翻译：适用于表面贴装去耦应用的多层陶瓷器件可以具有单个电容器或电容器阵列。该装置具有在其外表面上限定多个电端子的电容器主体。端子相互交错，使得相应的第一极性端子将与相应的第二极性端子相邻（反之亦然）。电容器主体包含相互间隔开的多个交错电容器板。第一极性的电容器板经由多个引线结构电连接到相应的第一极性端子。同样地，多个引线结构将第二极性的电容器板电连接到相应的第二极性端子。

8. 发明授权

US5032558A Electrostrictive ceramic material including a process for the preparation thereof and applications thereof 失效
标题翻译：电致伸缩陶瓷材料，包括其制备方法及其应用
公开(公告)号：US5032558A
公开(公告)日：1991-07-16
申请号：US443677
申请日：1989-11-30
申请人： Alex E. Bailey , Stephen R. Winzer , Audrey E. Sutherland , Andrew P. Ritter
发明人： Alex E. Bailey , Stephen R. Winzer , Audrey E. Sutherland , Andrew P. Ritter
IPC分类号： C04B35/472 , C04B35/497 , H01L41/187 , H01L41/24
CPC分类号： C04B35/472 , C04B35/497 , H01L41/1875 , H01L41/43
摘要： The invention relates to new ceramic electrostrictive compositions having superior electrical properties, a process for the preparation of the new electrostrictive compositions and applications for the new compositions. Specifically, a solid solution composition of lead magnesium niobate-lead titanate - (barium titanate or stronium titanate) has exhibited desirable electrostrictive properties. This composition shows a diminished dependence of dielectric constant on temperature.
摘要翻译：本发明涉及具有优异电性能的新型陶瓷电致伸缩组合物，制备新的电致伸缩组合物的方法和新组合物的应用。具体来说，铌酸铅镁铅钛酸盐（钛酸钡或钛酸锶）的固溶体组合物具有理想的电致伸缩性。该组成显示了介电常数对温度的依赖性的降低。

9. 发明授权

US08045319B2 Controlled ESR decoupling capacitor 有权
标题翻译：受控ESR去耦电容
公开(公告)号：US08045319B2
公开(公告)日：2011-10-25
申请号：US12135536
申请日：2008-06-09
申请人： Andrew P. Ritter , Marianne Berolini , Kimberly L. VanAlstine
发明人： Andrew P. Ritter , Marianne Berolini , Kimberly L. VanAlstine
IPC分类号： H01G4/005 , H01G4/228 , H01G4/06
CPC分类号： H01G4/232 , H01G2/06 , H01G4/30 , H01G4/35 , H05K1/0231 , Y10T29/435
摘要： Disclosed are apparatus and methodology for providing controlled equivalent series resistance (ESR) decoupling capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Controlled equivalent series resistance (ESR) is provided by providing extended length tab connections to active electrode layers within the device.
摘要翻译：公开了用于提供具有广泛适用于信号和功率滤波技术的受控等效串联电阻（ESR）去耦电容器设计的装置和方法。这种电容器设计提供了用于涉及信号电平和功率级环境的去耦应用的特性。通过为器件内的有源电极层提供延长长度的接头连接来提供受控的等效串联电阻（ESR）。

10. 发明申请

US20090147440A1 LOW INDUCTANCE, HIGH RATING CAPACITOR DEVICES 审中-公开
标题翻译：低电感，高额定电容器件
公开(公告)号：US20090147440A1
公开(公告)日：2009-06-11
申请号：US12329129
申请日：2008-12-05
申请人： Stanley P. Cygan , Andrew P. Ritter , John L. Galvagni
发明人： Stanley P. Cygan , Andrew P. Ritter , John L. Galvagni
IPC分类号： H01G4/228
CPC分类号： H01G4/232 , H01G4/38 , H05K1/0231 , H05K3/3426 , H05K2201/10515 , H05K2201/1053 , H05K2201/10636 , Y02P70/611 , Y10T29/43
摘要： Methodologies and structures are disclosed for providing multilayer electronic devices having low inductance and high ratings, such as for capacitor devices for uses involving faster pulsing and higher currents. Plural layer devices are constructed for relatively lowered inductance by relatively altering typical orientation of capacitors such that their electrodes are placed into a vertical position relative to an associated circuit board. Optionally, individual leads may be formed so that the resulting structure can be used as an array. Internal electrodes may be arranged for reducing current loops for associated circuits on a circuit board, to correspondingly reduce the associated inductance of the circuit board mounted device. Leads associated with such devices may have added tab-like structures which serve to more precisely place the lead, to improve the lead to capacitor strength, and to promote lower resistance and inductance. Disclosed designs for reducing associated inductance may be practiced in conjunction with various electric devices, including capacitors, resistors, inductors, or varistors.
摘要翻译：公开了用于提供具有低电感和高额定值的多层电子器件的方法和结构，例如用于涉及更快脉冲和较高电流的用途的电容器器件。通过相对地改变电容器的典型取向使得它们的电极相对于相关联的电路板被放置在垂直位置，多层器件被构造用于相对降低的电感。可选地，可以形成各个引线，使得所得到的结构可以用作阵列。可以布置内部电极以减少用于电路板上的相关电路的电流回路，以相应地减小电路板安装的装置的相关电感。与这种装置相关联的引线可以具有附加的片状结构，其用于更精确地放置引线，以改善导致电容器强度，并且促进较低的电阻和电感。用于减小相关电感的公开的设计可以结合包括电容器，电阻器，电感器或变阻器的各种电气设备来实施。

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